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MPC8240 Integrated Processor Hardware Specifications

System Design Information

interface connects primarily through the JTAG port of the processor, with some additional status monitoring

signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control

the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,

power supply failures, or push-button switches, the COP reset signals must be merged into these signals with

logic.

The arrangement shown in Figure 25 allows the COP to independently assert HRESET or TRST, while

ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,

TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted

ensuring that the JTAG scan chain is initialized during power-on.

The COP header shown in Figure 25 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header).

There is no standardized way to number the COP header shown in Figure 25; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 25 is common to all known emulators.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
KXPC8240LZU200E	制造商:Freescale Semiconductor 功能描述:
KXPC8240RVV250E	功能描述:IC MPU INTEGRATED 250MHZ 352TBGA RoHS:是類別:集成電路 (IC) >> 嵌入式 - 微處理器系列:MPC82xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29）包裝:托盤
KXPC8250AZUPHBA	制造商:Motorola Inc 功能描述:
KXPC8255CVVIFBC	功能描述:微處理器 - MPU PQ 2 HIP 3 NO-PB RoHS:否制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
KXPC8255CZUIFBC	功能描述:微處理器 - MPU POWERQUICC II HIP3 REV C RoHS:否制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

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