參數(shù)資料
型號(hào)： KXPC8240LVV200E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 0K
描述： IC MPU INTEGRATED 250MHZ 352TBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 200MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 352-LBGA
供應(yīng)商設(shè)備封裝： 352-TBGA（35x35）
包裝： 托盤
36
MPC8240 Integrated Processor Hardware Specifications
System Design Information
Figure 24. PLL Power Supply Filter Circuit
1.7.2
Power Supply Sizing
The power consumption numbers provided in Table 5 do not reflect power from the OVDD and GVDD power
supplies that are non-negligible for the MPC8240. In typical application measurements, the OVDD power
ranged from 200 to 600 mW and the GVDD power ranged from 300 to 900 mW. The ranges’ low-end power
numbers were results of the MPC8240 performing cache-resident integer operations at the slowest
frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. The OVDD high-end range’s value resulted
from the MPC8240 performing continuous flushes of cache lines with alternating ones and zeros to PCI
memory. The GVDD high-end range’s value resulted from the MPC8240 operating at the fastest frequency
combination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with
alternating ones and zeros on 64-bit boundaries to local memory.
1.7.3
Decoupling Recommendations
Due to its dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC8240 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8240 system, and the MPC8240 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, GVDD, and LVDD pin of the MPC8240. It is also recommended that these decoupling capacitors
receive their power from separate VDD, OVDD, GVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface
mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603,
oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.7.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to
GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, LVDD, and GND pins of the
MPC8240.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8240.
VDD
AVDD
10
2.2 F
GND
Low ESL Surface Mount Capacitors
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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