AVDD2
參數(shù)資料
型號： KXPC8240LVV200E
廠商： Freescale Semiconductor
文件頁數(shù)： 27/52頁
文件大?。?/td> 0K
描述： IC MPU INTEGRATED 250MHZ 352TBGA
標準包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 200MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 352-LBGA
供應商設(shè)備封裝： 352-TBGA（35x35）
包裝： 托盤
MPC8240 Integrated Processor Hardware Specifications
33
Package Description
AVDD2
AF24
Power for
PLL
(peripheral
logic) 2.5 V
AVDD2—
Manufacturing Pins
DA2
C25
Output
OVDD
DRV_PCI
2
DA[11:13]
AD26 AF17 AF19
Output
OVDD
DRV_PCI
2, 6
DA[14:15]
F1 J2
Output
GVDD
DRV_MEM_
ADDR
2, 6
Notes:
1. Place pull-up resistors of 120
or less on the TEST0 pin.
2. Treat these pins as no connects unless using debug address functionality.
3. This pin has an internal pull-up resistor that is enabled only when the MPC8240 is in the reset state. The value of
the internal pull-up resistor is not guaranteed but is sufficient to ensure that a 1 is read into configuration bits during
reset.
4. This pin is a reset configuration pin.
5. DL[0] is a reset configuration pin and has an internal pull-up resistor that is enabled only when the MPC8240 is in
the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a one is
read into configuration bits during reset.
6. Multi-pin signals such as AD[0:31] or DL[0:31] have their physical package pin numbers listed in order
corresponding to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22,...AD31 is on pin V25.
7. GNT4 is a reset configuration pin and has an internal pull-up resistor that is enabled only when the MPC8240 is in
the reset state.The value of the internal pull-up resistor is not guaranteed but is sufficient to ensure that a one is
read into configuration bits during reset.
8. Recommend a weak pull-up resistor (2–10 k
) be placed on this PCI control pin to LVDD.
9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
10.Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to OVDD.
11.Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to GVDD.
12.This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient
to prevent unused inputs from floating.
13.Output valid specifications for this pin are memory interface mode dependent (registered or flow-through), see
14.Non-DRAM access output valid specification applies to this pin during non-DRAM accesses, see specification 12b3
15.This pin is affected by programmable PCI_HOLD_DEL parameter, see Section 1.4.2.4.1, “PCI Signal Output Hold
16.This pin is an open drain signal.
17.This pin can be programmed to be driven (default) or can be programmed to be open drain; see the PMCR2 register
description in the MPC8240 Integrated Processor User’s Manual, for details.
18.This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.
19.Maximum input voltage tolerance is LVDD-based. See Table 2 for details.
Table 17. MPC8240 Pinout Listing (continued)
Name
Pin Number
Pin Type
Power
Supply
Output
Driver
Type
Notes
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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