參數(shù)資料
型號(hào): KM416S1020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM(512K x 16位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 為512k × 16 × 2銀行同步DRAM(為512k × 16位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 5/42頁(yè)
文件大小: 582K
代理商: KM416S1020C
KM416S1020C
CMOS SDRAM
- 6 -
Rev. 0.4 (Apr. 1998)
1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM416S1020CT-G**
4. KM416S1020CT-F**
Notes :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-7
-8
-H
-L
-10
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
OL
= 0 mA
95
95
90
90
80
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 15ns
1
mA
I
CC2
PS
CKE & CLK
V
IL
(max), t
CC
=
1
Precharge standby current in
non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
15
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
4
Active standby current in
power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 15ns
2
mA
I
CC3
PS
CKE & CLK
V
IL
(max), t
CC
=
1
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
25
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
15
mA
Operating current
(Burst mode)
I
CC4
I
OL
= 0 mA
Page burst
2Banks activated
t
CCD
= 2CLKs
3
140
130 115
115
115
mA
1
2
100
100 115
100
100
Refresh current
I
CC5
t
RC
t
RC
(min)
90
90
90
90
80
mA
2
Self refresh current
I
CC6
CKE
0.2V
1
mA
3
250
uA
4
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