參數(shù)資料
型號(hào): KM416S1020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM(512K x 16位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 為512k × 16 × 2銀行同步DRAM(為512k × 16位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 30/42頁(yè)
文件大?。?/td> 582K
代理商: KM416S1020C
TIMING DIAGRAM - I
CMOS SDRAM
ELECTRONICS
REV. 4 Nov. '97
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Page Read & Write Cycle at Same Bank @Burst Length=4
HIGH
Row Active
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
RDL
before Row precharge, will be written.
Read
(A-Bank)
tRCD
*Note 2
tRDL
*Note 1
*Note 3
tCDL
Qa0
Qa1
Qb0
Qb1
Qb2
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Dc0
Dc1
Dd0
Dd1
Write
(A-Bank)
BA
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Ra
Ca0
Cb0
Cc0
Cd0
Ra
相關(guān)PDF資料
PDF描述
KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interfacer(512K x 16位 x 2組同步動(dòng)態(tài)RAM(帶SSTL接口))
KM416S4020B 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動(dòng)態(tài)RAM)
KM416S4021B 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動(dòng)態(tài)RAM)
KM416S4030B 1M x 16Bitx 4 Banks Synchronous DRAM(1M x 16位 x4組同步動(dòng)態(tài)RAM)
KM416S4031B 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface(1M x 16位 x4組同步動(dòng)態(tài)RAM(帶SSTL接口))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM416S1020CTG10 制造商:n/a 功能描述:KM416S1020CT-G10 制造商:Samsung Semiconductor 功能描述:
KM416S1020CT-G10 制造商:n/a 功能描述:KM416S1020CT-G10 制造商:Samsung Semiconductor 功能描述:
KM416S1020CT-G10M 制造商:MAJOR 功能描述:
KM416S1021C 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
KM416S1021CT-G7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface