參數(shù)資料
型號(hào)： JTSX8388B-1V1B
英文描述： A/D CONVERTER
中文描述： 的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 5/45頁(yè)
文件大?。?/td> 1597K
代理商： JTSX8388B-1V1B
JTS8388B
5
Product Specification
3.3.
ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = -5 V ; V
CC
= +5 V ; V
IN
-V
INB
= 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50
differentially terminated ;
Tj (typical) = 70
°
C. Full temperature range : up to -55
°
C < Tj < +125
°
C
Parameter
Symb
Temp
Test
level
Min
Typ
Max
Unit
POWER REQUIREMENTS
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
VCC
V
PLUSD
V
PLUSD
II,IV
4.75
1.4
5
0
2.4
5.25
2.6
V
V
V
Positive supply current
Analog
Digital
ICC
I
PLUSD
II, IV
385
115
445
145
mA
mA
Negative supply voltage
VEE
Full
IV
-5.25
-5
-4.75
V
Negative supply current
Analog
Digital
AIEE
DIEE
II,IV
165
135
200
180
mA
mA
Nominal power dissipation
PD
Full
II
IV
3.4
4.1
4.1
4.3
W
W
Power supply rejection ratio
(note 2)
PSRR
IV
+/- 0.5
mV/V
RESOLUTION
8
bits
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage )
V
IN
V
INB
Full
IV
-125
-125
125
125
mV
mV
Full Scale Input Voltage range (single–ended input option )
(see Application
Notes)
V
IN
V
INB
Full
IV
-250
0
250
mV
mV
Analog input capacitance
C
IN
Full
IV
0.4
pF
Input bias current
I
IN
Full
IV
10
μ
A
Input Resistance
R
IN
Full
IV
1
M
Full Power input Bandwidth
FPBW
Full
IV
1.8
GHz
Small Signal input Bandwidth (10 % full scale)
SSBW
Full
IV
1.9
GHz
CLOCK INPUTS
Logic compatibility for clock inputs
(see Application Notes)
(note 10 )
ECL or specified clock input
power level in dBm
ECL Clock inputs voltages (V
CLK
or V
CLKB
) :
Full
IV
Logic “0” voltage
V
IL
-1.5
V
Logic “1” voltage
V
IH
-1.1
V
Logic “0” current
I
IL
5
μ
A
Logic “1” current
I
IH
5
μ
A
Clock input power level into 50
termination
DBm into 50
Clock input power level
Full
IV
-2
4
10
dBm
Clock input capacitance
C
CLK
Full
IV
0.4
3.5
pF
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