參數(shù)資料
型號(hào)： JTSX8388B-1V1B
英文描述： A/D CONVERTER
中文描述： 的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 2/45頁(yè)
文件大?。?/td> 1597K
代理商： JTSX8388B-1V1B
2
JTS8388B
Product Specification
TABLE OF CONTENTS
1.
SIMPLIFIED BLOCK DIAGRAM.......................................................................................................................................... 3
2.
FUNCTIONAL DESCRIPTION .............................................................................................................................................. 3
3.
SPECIFICATIONS.................................................................................................................................................................... 4
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
ABSOLUTE MAXIMUM RATINGS (
SEE NOTES BELOW
)..................................................................................................................................4
RECOMMENDED CONDITIONS OF USE .....................................................................................................................................................4
ELECTRICAL OPERATING CHARACTERISTICS.........................................................................................................................................5
T
IMING
D
IAGRAMS
.............................................................................................................................................................................................9
EXPLANATION OF TEST LEVELS ..............................................................................................................................................................10
WAFER SCREENING...................................................................................................................................................................................10
FUNCTIONS DESCRIPTION........................................................................................................................................................................11
DIGITAL OUTPUT CODING.........................................................................................................................................................................11
4.
PACKAGE DESCRIPTION................................................................................................................................................... 13
4.1.
4.2.
4.3.
4.4.
JTS8388B PIN DESCRIPTION.....................................................................................................................................................................13
JTS8388B CHIP PAD LIST, COORDINATES AND CORRESPONDING FUNCTIONS...............................................................................14
JTS8388B CHIP PADS DESIGNATION VH25B...........................................................................................................................................15
DIE MECHANICAL INFORMATIONS...........................................................................................................................................................16
5.
TYPICAL CHARACTERIZATION RESULTS................................................................................................................... 17
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MH
Z
.................................................................................................................................17
EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION .............................................................................................18
TYPICAL FFT RESULTS..............................................................................................................................................................................19
SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE........................................................................................................20
DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY .....................................................................................................21
EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY..........................................................................................22
SFDR VERSUS SAMPLING FREQUENCY .................................................................................................................................................22
JTS8388B ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE..............................................................................................23
TYPICAL FULL POWER INPUT BANDWIDTH ............................................................................................................................................24
ADC STEP RESPONSE...........................................................................................................................................................................25
6.
DEFINITION OF TERMS...................................................................................................................................................... 26
7.
APPLYING THE JTS8388B................................................................................................................................................... 28
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
TIMING INFORMATIONS.............................................................................................................................................................................28
PRINCIPLE OF DATA READY SIGNAL CONTROL BY
DRRB INPUT COMMAND....................................................................................29
ANALOG INPUTS (VIN) (VINB)....................................................................................................................................................................29
CLOCK INPUTS (CLK) (CLKB) ....................................................................................................................................................................30
CLOCK SIGNAL DUTY CYCLE ADJUST.....................................................................................................................................................32
NOISE IMMUNITY INFORMATIONS............................................................................................................................................................32
DIGITAL OUTPUTS......................................................................................................................................................................................33
OUT OF RANGE BIT ....................................................................................................................................................................................36
GRAY OR BINARY OUTPUT DATA FORMAT SELECT..............................................................................................................................36
TS8388 B THERMAL REQUIREMENTS..................................................................................................................................................36
DIODE PAD 32.........................................................................................................................................................................................37
ADC GAIN CONTROL PAD 38 ................................................................................................................................................................37
8.
EQUIVALENT INPUT / OUTPUT SCHEMATICS ............................................................................................................ 38
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS........................................................................................................38
EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS...........................................................................................38
EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS..........................................................................................39
ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS....................................................................................39
GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS......................................................................................................40
DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS......................................................................................................40
9.
TSEV8388B : DEVICE EVALUATION BOARD................................................................................................................. 42
10.
ORDERING INFORMATION ........................................................................................................................................... 43
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