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參數(shù)資料
| 型號(hào)： | JTSX8388B-1V1B |
| 英文描述： | A/D CONVERTER |
| 中文描述： | 的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 32/45頁 |
| 文件大小： | 1597K |
| 代理商： | JTSX8388B-1V1B |
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32
JTS8388B
Product Specification
7.5.
CLOCK SIGNAL DUTY CYCLE ADJUST
At fast sampling rates, ( 1 Gsps and above), the device performance ( especially the SNR ) may be improved by tuning the Clock duty cycle
(CLK,CLKB).
In single ended configuration, when using a sinewave clock generator, the clock signal duty cycle can be easily adjusted by simply offseting the
inphase clock signal using a biasing tee, (as the out of phase clock input is at ground level ).
Single ended Clock input (Inphase clock input common mode shifted)
VCLK common mode = -180mV
VCLKB = 0 Volt
[V]
t
VCLK - 180 mV
VCLKB = ( 0 V )
-0.5V
40 %
60 %
+0.5V
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
Note 2 : For an input CLK signal of 4 dBm into 50 ohms, the typical offset value to achieve a 40 / 60 clock duty cycle is -180 mV on CLK.
7.6.
NOISE IMMUNITY INFORMATIONS
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the
circuit itself or induced by external circuitry.
(Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.)
Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise
rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs :
The analog inputs and clock inputs of the TS8388B device have been surrounded by ground pins, which must be directly connected to the external
ground plane.
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