參數資料
型號： JTSX8388B-1V1B
英文描述： A/D CONVERTER
中文描述： 的A / D轉換器
文件頁數： 14/45頁
文件大?。?/td> 1597K
代理商： JTSX8388B-1V1B
14
JTS8388B
Product Specification
4.2.
JTS8388B CHIP PAD LIST, COORDINATES AND CORRESPONDING FUNCTIONS
Pad
number
1
2
PosX
PosY
Chip pad
function
V
PLUSD
D5
880
670
1365
1365
Positive digital supply
In phase (+) digital output, bit 5
D0 is the LSB ; Bit 0)
Inverted phase (-)digital output, bit 5
In phase (+) digital output, bit 4
Inverted phase (-) digital output, bit 4
-5V digital supply
In phase (+) Data Ready
Inverted Phase (-) Data Ready
In phase (+) digital output, bit 3
Inverted phase (-) digital output, bit 3
Positive digital supply
In phase (+) digital output, bit 2
Inverted phase (-) digital output, bit 2
In phase (+) digital output, bit 1
Inverted phase (-) digital output, bit 1
In phase (+) digital output, bit 0, Least Significant Bit
Inverted phase (-) digital output, bit 0, Least Significant Bit
Gray or Binary data output format select.
2)
+5V supply
Analog Ground
+5V supply
-5V analog supply
+5V supply
Analog Ground
In phase (+) clock input
Analog Ground
Inverted phase (-) clock input
Analog Ground
-5V analog supply
+5V supply
-5V analog supply
Diode input for Tj monitoring / Input for asynchronous Data
Ready Reset
Analog Ground
In phase (+) analog input
Analog Ground
Inverted phase (-) analog input
Analog Ground
ADC gain adjust input
+5V supply
+5V supply
In phase (+) Out of Range digital output
Inverted phase (-) Out of Range digital output
In phase (+) digital output, bit 7, Most Significant Bit
Inverted phase (-) digital output bit 7
In phase (+) digital output, bit 6
Inverted phase (-) digital output, bit 6
(double pad) (note 3)
(D7 is the MSB ; Bit 7,
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
510
350
190
-20
-230
-390
-550
-710
-920
-1085
-1085
-1085
-1085
-1085
-1085
-1085
1365
1365
1365
1365
1365
1365
1365
1365
1365
1115
955
795
635
475
315
155
D5B
D4
D4B
DV
EE
DR
DRB
D3
D3B
V
PLUSD
D2
D2B
D1
D1B
D0
D0B
GORB
(double pad)
(double pad) (note 3)
(Note
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-1085
-1085
-1085
-1085
-1085
-905
-655
-455
-255
-5
245
495
745
945
-55
-325
-595
-865
-1135
-1365
-1365
-1365
-1365
-1365
-1365
-1365
-1365
-1365
V
CC
GND
V
CC
V
EE
V
CC
GND
CLK
GND
CLKB
GND
V
EE
V
CC
V
EE
DIOD/DRRB
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
(double pad)
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1085
1085
1085
1085
1085
1085
1085
1085
1085
1085
1085
1085
1085
1085
-1195
-995
-795
-595
-345
-145
55
265
425
585
745
905
1065
1225
GND
V
IN
GND
V
IN
B
GND
GAIN
V
CC
V
CC
OR
ORB
D7
D7B
D6
D6B
(double pad)
(double pad)
(double pad)
(double pad)
Note 1 : Coordinates are relative to pad centers. The coordinates origin (0,0) is at the center of the die.
All dimensions are given in microns. The pad 1 is the one pointed at by the arrow (see layout).
Distance between pad (glass window) and inner edge of seal-ring : 40μm.
Die size (inner edge of seal-ring : (-1175, -1175, 1455).
Die size (including scribe line) : (-1230, -1510) (1230, 1510) (2.46 x 3.02 mm2).
Actual die size (after separation) : (-1220, -1500) (1220, 1500) (2.44 mm x 3.00 mm).
Note 2 : GORB tied to Vcc or floating : Binary output data format. GORB tied to GND : Gray output data format
Note3 : The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply
level in the name proportion in order to spare power dissipation.
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