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參數(shù)資料
| 型號(hào)： | JTSX8388B-1V1B |
| 英文描述： | A/D CONVERTER |
| 中文描述： | 的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 31/45頁 |
| 文件大?。?/td> | 1597K |
| 代理商： | JTSX8388B-1V1B |
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JTS8388B
31
Product Specification
Single ended Clock input (Ground common mode)
VCLK common mode = 0 Volt
VCLKB=0 Volt
4 dBm typical clock input power level
(into 50 ohms termination resistor)
[V]
+0.5V
t
VCLK
VCLKB = ( 0 V )
-0.5V
CLK or CLKB
50
(external)
50
reverse termination
1M
0.4 pF
CLK or CLKB double pad (25, 27)
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
7.4.2.
DIFFERENTIAL ECL CLOCK INPUT
The clock inputs can be driven differentially with nominal -0.8V / -1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to
obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels.
Note : As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out
of phase especially at fast clock rates in the GSPS range.
Differential Clock inputs (ECL Levels)
-0.8V
[mV]
t
-1.8V
VCLKB
VCLK
Common mode = -1.3 V
CLK or CLKB
50
reverse termination
1M
0.4 pF
-2V
50
(external)
CLK or CLKB double pad (25, 27)
7.4.3.
SINGLE ENDED ECL CLOCK INPUT
In single–ended configuration enter on CLK ( resp. CLKB ) pin , with the inverted phase Clock input pin CLKB (respectively CLK) connected to -1.3V
through the 50 ohms termination resistor.
The inphase input amplitude is 1 Volt peak to peak, centered on -1.3 Volt common mode.
Single ended Clock input (ECL):
VCLK common mode = -1.3 Volt.
VCLKB = -1.3 Volt
-0.8V
[V]
t
-1.8V
VCLK
VCLKB = -1.3 V
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