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參數(shù)資料
| 型號： | ISL5217EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | 四可編程轉(zhuǎn)換器 |
| 文件頁數(shù)： | 36/43頁 |
| 文件大?。?/td> | 766K |
| 代理商： | ISL5217EVAL1 |
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36
TABLE 41. I AND Q CHANNEL COEFFICIENTS (15:0)
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x100-0x1ff (PAGE 1)
BIT
FUNCTION
DESCRIPTION
15:0
Filter coefficient
256 location RAM. Use this page when the I and Q coefficients are different.
NOTES:
Coefficients
RAM Read/Write Procedure (16-bit 2’s complement format)
Write
access to the Coefficient RAMs when I not equal Q:
1. Enable the
μ
P hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14 with the Q coefficient
3. Load the RAM data to location 0x14 with the I coefficient
4. Load the RAM write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the RAM location
specified by the contents of the register at location 0x15. (Indirect address[15] =0, Indirect address[9:8]=”01”).
5. Wait 4 clock cycles before performing the next write to the RAM data register.
6. Repeat steps 2-5.
7. Return RAM control back to the channel by disabling the
μ
P hold mode.
Read
access to the I Coefficient RAM:
1. Enable the
μ
P hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register
at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8]=”01”).
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. Repeat steps 2-3.
5. Return RAM control back to the channel by disabling the
μ
P hold mode.
Read
access to the Q Coefficient RAM:
1. Enable the
μ
P hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register
at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8] =’10’).
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. After all data has been loaded, return RAM control back to the channel by disabling the
μ
P hold mode
Coefficients
RAM Read/Write Procedure (24-bit floating point format)
Write
access to the Coefficient RAMs:
1. Enable the
μ
P hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14 with the iCoef<3:0>, iShift<3:0>, qCoef<3:0>, qShift<3:0>.
3. Load the RAM data to location 0x14 with the qCoef<19:4>.
4. Load the RAM data to location 0x14 with the iCoef<19:4>.
5. Load the RAM write address to location 0x15. A write strobe transfers the contents of the three previously loaded registers at location 0x14
into the RAM location specified by the contents of the register at location 0x15. (Indirect address[15] =0, Indirect address[9:8] =’01’).
6. Wait 4 clock cycles before performing the next write to the RAM data register.
7. Repeat steps 2-6.
8. Return RAM control back to the channel by disabling the
μ
P hold mode.
Read
access to the Coefficient RAM:
1. Enable the
μ
P hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. Three read strobes are required to transfers the contents of the RAM location specified by the
contents of the register at location 0x15 onto the read bus. Indirect address[15] =1, Indirect address[9:8] =’01’, reads back the iCoef value,
Indirect address[15] =1, Indirect address[9:8] =’10’, reads back the qCoef value, Indirect address[15] =1, Indirect address[9:8] =’11’, reads
back the iCoef<3:0>, iShift<3:0>, qCoef<3:0>, qShift<3:0> value.
3. Wait 4 clock cycles between all of the above writes before performing the next write to the Ram address register.
4. Repeat steps 2-3.
5. Return RAM control back to the channel by disabling the
μ
P hold mode.
ISL5217
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