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參數(shù)資料
| 型號： | ISL5217EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | 四可編程轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大?。?/td> | 766K |
| 代理商： | ISL5217EVAL1 |
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11
Polyphase output 1 = (D1*D[n]) + (D5*D[n-1]) + (D9*D[n-2])
+ (D13*D[n-3])
Polyphase output 2 = (D2*D[n]) + (D6*D[n-1]) + (D10*D[n-2])
+ (D14*D[n-3])
Polyphase output 3 = (D3*D[n]) + (D7*D[n-1]) + (D11*D[n-2])
+ (D15*D[n-3])
Table 4 details the coefficient address allocation for the
previous example. The interpolation phase is on the left and
the data span is across the top. The coefficient RAM address
followed by the coefficient term is listed in the table’s cell.
Table 49 details the coefficient address locations through
255.
The loading options are programmable including read back
modes and are discussed in detail in the ‘Microprocessor
Interface’ section. Both 16-bit 2’s complement and 24-bit
floating point format are allowed. The 2’s complement
coefficient format of valid digital values ranges from 0x8001
to 0x7FFF. The value 8000 is not allowed. The 24-bit floating
point (20-bit mantissa with 4-bit exponent) mode allows an
exponent range from 0 to 15. An exponent of 0 indicates
multiplication of the coefficient by 2
0
, and an exponent of 1 is
2
-1
, down to a value of 15 being 2
-15
. The default mode is 2’s
complement, with 24-bit floating point mode enabled by
setting control word (0x17, bit 12).
The gain through the filter is:
A = (sum of coefficients) / interpolation rate.
The shaping filter contains saturation logic in the event that
the final output peaks over +/- 1.0. When using quadrature
modulation, saturation/overflow can occur when the input
values for I and Q exceed 0.707 peak. The shaping filter
coefficients may need to be reduced from full scale to
prevent saturation.
Gain Profile
The overall channel gain is controlled by both a gain profile
stage and a gain control stage, which provide identical scaling
for the I and Q upconverted data. The gain profile stage allows
transmit ramp-up and quench fading, to control the sidelobe
profile in burst mode. This is implemented through user control
of the rise and fall transitions utilizing a gain profile memory.
The gain profile memory is a 128 x 12 bit RAM which is loaded
with the desired scaling coefficients via indirect addressing of
memory spaces 0x000-0x07f. The pulse shaping is
implemented by linearly multiplying the programmed coefficient
by the shaping filter outputs at the f
S
*IP or coarse phase rate.
The gain profile is enabled by FIR control (0xd, bit 15), with the
RAM address pointer being reset to zero on assertion of the
gain profile enable. Control of the pulse shaping is based on
TXENX, as the TXENX rising edge causes the RAM pointer to
begin stepping through the profile until the RAM pointer
matches the Gain profile length programed into control word
(0x0b, bits 6:0). The falling edge of TXENX reverses the
process and the RAM pointer begins decrementing until it
reaches zero. The gain process is symmetric with respect to the
rising or falling edges of TXENX. The latency through the gain
profile block is set by control word (0x0b, bits 8:7) where bit 8
bypasses all latency alignment circuitry and uses TXENX as
input to the channel. Setting control word (0x0b, bit 7) removes
two edge latencies from the delay path and should be
combined with selection of DS = 3, IP = 4 in order to have
perfect symmetry through the gain profile block. The memory
coefficients may be loaded without taking the channel off-line.
This is implemented by setting the gain profile hold bit in control
word (0x0c, bit 14) which holds the last gain value and provides
access to the memory.
The gain profile coefficients are programmed as unsigned
values:
Bit weight 2
0
.2
-1
2
-2
... 2
-11
Maximum 0x800 = 1.0
0x001 = 2
-11
Minimum 0x000 = 0.0
TABLE 4. ADDRESS ALLOCATION
DS [n]
DS [n-1]
DS [n-2]
DS [n-3]
IP0
0
CO
16 C4
32 C8
48 C12
IP1
1
C1
17 C5
33 C9
49 C13
IP2
2
C2
18 C6
34 C10
50 C14
IP3
3
C3
19 C7
35 C11
51 C15
IP4
4
20
36
52
IP5
5
21
37
53
IP6
6
22
38
54
IP7
7
23
39
55
IP8
8
D0
24 D4
40 D8
56 D12
IP9
9
D1
25 D5
41 D9
57 D13
IP10
10 D2
26 D6
42 D10
58 D14
IP11
11 D3
27 D7
43 D11
59 D15
IP12
12
28
44
60
IP13
13
29
45
61
IP14
14
30
46
62
IP15
15
31
47
63
ISL5217
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參數(shù)描述 |
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| ISL5217KI | 功能描述:上下轉(zhuǎn)換器 196BGA,-40+85C PROGRAMMABLE QUAD UP CONVERTER RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| ISL5217KIZ | 制造商:Intersil Corporation 功能描述:UP/DOWN CONV MIXER 2.5V 196BGA - Trays 制造商:Intersil 功能描述:W/ANNEAL 196BGA -40+ 85C PROG CONVER |
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| ISL5239EVAL1 | 功能描述:EVALUATION BOARD FOR ISL5239 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| ISL5239KI | 功能描述:音頻 DSP PA LINEARIZER IND TEMP 1 0MM PITCH RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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