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參數(shù)資料
| 型號： | ISL5217EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | 四可編程轉(zhuǎn)換器 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 766K |
| 代理商： | ISL5217EVAL1 |
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34
NOTES:
29. When in the QASK mode, the I and Q symbols will not be moved into the FIFO until both have been received.
30. When in the FM mode, the I symbol is moved to the FIFO after it has been shifted in.
31. The order of the I and Q symbols is based on the I and Q time slot values.
TABLE 35. Q - SERIAL TIME SLOT (Continued)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x13
BIT
FUNCTION
DESCRIPTION
TABLE 36. RAM DATA (15:0)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x14
BIT
FUNCTION
DESCRIPTION
15:0
RAM Data
Indirect data port for the Gain profile, I and Q coefficients RAMs.
TABLE 37. RAM ADDRESS (15:0)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x15
BIT
FUNCTION
DESCRIPTION
15:0
RAM Address
Indirect address port for the Gain profile, I and Q coefficients RAMs. The MSB determines the type of
access.
1 = read 0 = write.
TABLE 38. STATUS (15:0)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x16
BIT
FUNCTION
DESCRIPTION
15:12
Reserved
Not Used.
11
Channel Flushed
Indicates zero valued data has propagated through the channel after entering the off-line mode. Counts
24 consecutive FIFO reads after deassertion of on-line control bit, Main Control, 0x0C, bit 6.
10
I FIR Overflow
I FIR accumulator output saturates to most positive value.
9
I FIR Underflow
I FIR accumulator output saturates to most negative value + 1.
8
Q FIR Overflow
Q FIR accumulator output saturates to most positive value.
7
Q FIR Underflow
Q FIR accumulator output saturates to most negative value + 1.
6:4
FIFO Read Address
<2:0>
FIFO read address range 0 to 7, 0 = empty, 7 = full.
3
FIFO Underflow
FIFO read address = 0, FIFO write =0, FIFO read =1.
2
FIFO Overflow
FIFO read address = 7.
1
FIFO Almost Empty
FIFO read address < Almost empty threshold.
0
FIFO Empty
FIFO read address = 0.
NOTES:
32. Status bits <10:7,3> are or’ed and latched by the Top
μ
P interface.
33. Status bits <11:0> are latched by the single channel
μ
P interface.
34. The status register is cleared by writing to the Top status register.
35. Detection of FIFO overflow puts the channel in the off-line mode.
36. The Channel flushed status is be asserted 24 sample clocks after entering the off-line mode.
ISL5217
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