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參數(shù)資料
| 型號： | ISL5217EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | 四可編程轉(zhuǎn)換器 |
| 文件頁數(shù)： | 30/43頁 |
| 文件大?。?/td> | 766K |
| 代理商： | ISL5217EVAL1 |
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TABLE 28. MAIN CONTROL
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0c
BIT
FUNCTION
DESCRIPTION
15
Immediate Update
(sc conf reg update)
0 = Allows the configuration slave registers to be synchronously updated based the update mask.
1 = Allows
μ
P writes to bypass the update mask and load the selected configuration slave register
immediately from the master, (requires 4 clk synchronization).
14
Gain Profile Hold
Allows
μ
P access to the gain profile RAM. Upon assertion the device will hold the last address and gain
value from the ramp. When deasserted, the gain profile RAM output returns to the ramp address and
value currently loaded. Normal access would be to re-load the coefficients with the gain profile RAM
ramping function having completed (either up or down).
0 = normal access by the hardware.
1 =
μ
P access for loading the gain profile coefficients.
13
Delay Select
0 = no delay.
1 = 1/2 coarse sample delay inserted in the I/Q path after the FIR.
12
μ
P Hold
Allows
μ
P access to the I and Q coefficient RAMs.
0 = normal access by the hardware.
1 =
μ
P access for loading filter coefficients.
11
TXENX Control
Set to one to enable the internal generation and control of TXENX based on the programmed values of
indirect registers 0x400-0x404 and 0x407. Set to zero (default) to input TXENX externally.
10:8
Almost Empty Threshold
(2:0)
Almost Empty Threshold (2:0). FIFO depth threshold (number of data samples in the FIFO - 1) at which
the Almost Empty flag will be asserted, alerting the data source that more input data is required in the
FIFO. The FIFO threshold sets both the I and Q FIFO thresholds. (2) is the MSB.
7
Complex Output Mode
Allows complex data out at the full rate when in 4-ch re output mode. The effect of this setting depends
on the channel.
CH 0 = Over-rides selection of re sum2 and selects im sum1 for output.
CH 1 = n/a.
CH 2 = Over-rides selection of re sum4 and selects im sum3 for output.
CH 3 = n/a.
6
On-Line Mode
0 = Off line - zeroes data from FIFO - (reset FIFO cntrl forces rd_addr to 0 which selects zero value data
for I and Q) This takes 24 sample-clocks to flush the channel. The status bit CH FLUSHED will be
asserted when complete.
1 = On line - allows normal operation of the IQ FIFO’s.
5
Input En
Enables input of selected hw TX_enable and hw Update.
4
Channel Output En
0 = Disables output of channel, clears data to zero.
1 = Enables output of channel. Passes data.
3
TXENX SIB Control
Disables TXENX control of the Serial Interface Block (SIB) and allows it to continue running independent
of the TXENX signal. Data input should be zeroed during TXENX low time, as the data will continue to be
processed by the SIB.
0 = normal TXENX control of SIB.
1 = TXENX SIB control disabled.
2
TXENX Channel Flush
Disables TXENX control of the channel flushing. Setting this bit will stop the device from flushing the
channel and FIR data RAM with zeroes upon the rising edge of TXENX.
0 = normal TXENX channel flushing.
1 = TXENX will not flush the channel.
1
FIFO Overflow Reset
Disables the FIFO overflow channel reset function. This is only applicable in the parallel input mode.
0 = normal FIFO overflow channel reset.
1 = FIFO overflow channel reset disabled.
0
Sw TX Enable
Rising edge flushes data RAM, (16 clks) and updates configuration slave registers as determined by the
update mask. High level allows serial requests to occur. Low level inhibits additional serial data requests,
(assertion TX frame strobe).
ISL5217
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