參數(shù)資料
型號(hào): ISL5217EVAL1
廠商: Intersil Corporation
英文描述: Quad Programmable Up Converter
中文描述: 四可編程轉(zhuǎn)換器
文件頁數(shù): 23/43頁
文件大?。?/td> 766K
代理商: ISL5217EVAL1
23
IIN<19:0> or QIN<19:0> Delay Time from CLK
t
IQIDC
2
7
ns
IOUT<19:0> or QOUT<19:0> Delay Time from CLK
t
IQODC
2
7
ns
IIN<19:0> or QIN<19:0> Valid Time from CLK, 2X Rate
t
IQVC2X
2
8
ns
IOUT<19:0> or QOUT<19:0> Valid Time from CLK, 2X Rate
t
IQVC2X
2
8
ns
SCLKX Valid Time from CLK, SCLX = CLK
t
SVC1X
2
7
ns
SCLKX Valid Time from CLK, SCLX = Divided CLK
tSVC
2
7
ns
ISTRB Delay Time from CLK
t
IDC
2
6
ns
FSRX Delay Time from CLK
t
FDC
-
7
ns
SYNCO Delay Time from CLK
t
SDC
-
9
ns
P<15:0> Delay Time from CLK
t
PDC
-
16
ns
P<15:0> Delay Time from A<6:0> or CS
t
PDAC
-
20
ns
P<15:0> Delay Time from A<6:0> or CS (RDMODE=1)
t
PDAC1
-
20
ns
Output Rise/Fall Time (Note 7)
t
RF
-
3
ns
NOTES:
6. AC tests performed with C
L
= 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
Test V
IH
= 3.0V, V
IHC
= 3.0V, V
IL
= 0V, V
OL
= 1.5V, V
OH
= 1.5V.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Electrical Specifications
V
CCC
= 2.5 ± 5%, V
CCIO
= 3.3 ± 5%, T
A
= -40
o
C to 85
o
C (Note 6)
(Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
AC Test Load Circuit
EQUIVALENT CIRCUIT
C
L
I
OH
1.5V
I
OL
DUT
SWITCH S
1
OPEN FOR I
CCSB
AND I
CCOP
S
1
±
TEST HEAD CAPACITANCE
Waveforms
FIGURE 19. CLOCK AND RESET TIMING
FIGURE 20. SERIAL INTERFACE RELATIVE TIMING
CLK
t
RSC
t
RPW
RESET
t
CH
t
CL
t
CLK
t
CLK
= 1 / F
CLK
t
RHC
CLK
SCLKX
FSRX
SDX
t
SSS
t
SHS
t
SVC
t
FDC
ISL5217
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