參數(shù)資料
型號: ISL5217EVAL1
廠商: Intersil Corporation
英文描述: Quad Programmable Up Converter
中文描述: 四可編程轉(zhuǎn)換器
文件頁數(shù): 25/43頁
文件大?。?/td> 766K
代理商: ISL5217EVAL1
25
Programming Information
FIGURE 27. MICROPROCESSOR READ TIMING (RDMODE = 0)
FIGURE 28. MICROPROCESSOR READ TIMING (RDMODE = 1)
Waveforms
(Continued)
RD
WR
A<6:0>
P<15:0>
CS
VALID
VALID
t
PDR
t
PER
t
PDAC
RD (RD/WR)
WR (DS)
A<6:0>
P<15:0>
CS
VALID
VALID
t
PDWR1
t
PEWR1
t
PDAC1
TABLE 10. ISL5217 MEMORY MAP
ADDRESS(6:0)
DEVICE MEMORY MAP
(000 0000) - (001 0111)
0x00 - 0x17
Channel 0
(001 1000) - (001 1111)
0x18 - 0x1f
Undefined
(010 0000) - (011 0111)
0x20-0x37
Channel 1
(011 1000) - (011 1111)
0x38 - 0x3f
Undefined
(100 0000) - (101 0111)
0x40-0x57
Channel 2
(101 1000) - (101 1111)
0x58 - 0x5f
Undefined
(110 0000) - (111 0111)
0x60-0x77
Channel 3
(111 1000) - (111 1111)
0x78-0x7f
Device control
NOTES:
8. Consecutive accesses to the same address require a 4 clock synchronized update to occur before beginning the next accesses.
9. Different direct address locations can be accessed without having to wait for a 4 clock synchronized update to occur.
10. All configuration registers have a master/slave architecture. The master registers are clocked by WR. The slave registers are clocked by CLK.
11. The master registers are writable and cleared by a hard reset. All master registers are located in the SC
μ
P block.
12. The slave registers are readable and cleared by either a hard or soft reset. Refer to the table to determine location of slave registers.
13. Partition indirect address space into pages of 256 words.
14. Decode indirect address <9:8> to determine page, (3 used).
15. Indirect address<14:10> are not used.
16. Indirect address<15> determines access type. 1=read; 0=write.
ISL5217
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