參數(shù)資料
型號： IDT5V9885TPFGI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 27/39頁
文件大?。?/td> 0K
描述： IC CLOCK GEN PLL 500MHZ 32TQFP
標準包裝： 250
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 無/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 管件
其它名稱： 800-2579
33
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
RAM (PROGRAMMING REGISTER) TABLES
ADDR
7
6
5
4
3
2
1
0
Default
Register
Hex Value
7
6
5
4
3
2
1
0
BIT #
(Default Settings)
DESCRIPTION
0x1F
0
00
INV1
0x20
0
00
ODIV1_CONFIG0
0x21
0
00
ODIV1_CONFIG1
0x22
0
00
ODIV1_CONFIG2
0x23
0
00
ODIV1_CONFIG3
0x24
0
00
0x25
0
00
0x26
0
00
0x27
0
00
0x28
0
00
0x29
0
00
0x2A
0
00
0x2B
0
00
0x2C
0
00
0x2D
0
00
0x2E
0
00
0x2F
0
00
0x30
0
00
0x31
0
00
0x32
0
00
0x33
0
00
0x34
0
1
0
1
0
46
PRIMCLK
0x35
0
1
0
1
0
1
0
1
55
SRC1[1:0]
SM[1:0]
SRC2[1:0]
OEM1[1;0]
SLEW1[1:0]
CP1[3:0]_CONFIG3
A1[3:0]_CONFIG2
N1[7:0]_CONFIG1
N1[7:0]_CONFIG3
D1[7:0]_CONFIG0
N1[11:8]_CONFIG0
CP1[3:0]_CONFIG2
D1[7:0]_CONFIG3
N1[7:0]_CONFIG0
CZ1[3:0]_CONFIG3
D1[7:0]_CONFIG2
CZ1[3:0]_CONFIG2
D1[7:0]_CONFIG1
CP1[3:0]_CONFIG1
CZ1[3:0]_CONFIG1
RZ1[3:0]_CONFIG2
SRC6[1:0]
SRC5[1:0]
SRC4[1:0]
CP1[3:0]_CONFIG0
IP1[2:0]_CONFIG2
N1[11:8]_CONFIG2
A1[3:0]_CONFIG3
N1[11:8]_CONFIG3
A1[3:0]_CONFIG1
N1[11:8]_CONFIG1
CZ1[3:0]_CONFIG0
RZ1[3:0]_CONFIG0
RZ1[3:0]_CONFIG3
RZ1[3:0]_CONFIG1
SRC3[1:0]
N1[7:0]_CONFIG2
A1[3:0]_CONFIG0
IP1[2:0]_CONFIG0
IP1[2:0]_CONFIG1
IP1[2:0]_CONFIG3
Configuring Output OUT1
INV1=Output Inversion for OUT1 ("0"= Non-Invert (Default), "1"=Invert);
SLEW1=Slew Rate Settings for OUT1 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM1= Output Enable Mode for OUT1 output, when used with OE1 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Address 0x1F, Bits 3, 1, 0 are reserved and should be set to "0"
PRIMCLK=Priority Selection for Input Clock ("0"=XTALIN/REF_IN becomes Primary (Default), "1"=CLK_IN becomes Primary);
SM = Switchover Mode ("0x"=Manual, "10"= Auto-NonRevertive, "11"=Auto-Revertive (Default));
Bit 3 is reserved and should be set to "0".
SRCx[1:0]=Input Source Selection for Output Dividers "Qx" blocks ("00"=Selected Input CLK, "01"=PLL0, "10"=PLL1, "11"=PLL2);
Default on SRC1 is the selected input clock. Default on SRC2-6 is PLL0 which will be powered down.
PLL1 LOOP FILTER SETTING
Loop Filter Values for PLL1 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV1_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated
with PLL1; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3K
+ RZ1[3:0] * 1K , 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ1[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP1[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP1[2:0] A, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
PLL1 INPUT DIVIDER D1 SETTING
PLL1 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL1 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N1[11:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A1[3:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET1[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x68-0x6F
Total Multiplier Value M1 = 2 * N1[11:0] + A1 + 1 + SS_OFFSET1 * 1/64
When A1[3:0] = 0 and spread spectrum disabled, M1= 2 * N1[11:0];
When A1[3:0] > 0 and spread spectrum disabled, M1 = 2 * N1[11:0] + A1 + 1 ;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
0x36
0x37
0x38
0
00
ODIV2_CONFIG0
0x39
0
00
ODIV2_CONFIG1
0x3A
0
00
ODIV2_CONFIG2
0x3B
0
00
ODIV2_CONFIG3
0x3C
0
00
0x3D
0
00
0x3E
0
00
0x3F
0
00
CP2[3:0]_CONFIG2
CP2[3:0]_CONFIG1
IP2[2:0]_CONFIG0
RZ2[3:0]_CONFIG1
IP2[2:0]_CONFIG1
RZ2[3:0]_CONFIG0
CZ2[3:0]_CONFIG1
IP2[2:0]_CONFIG3
IP2[2:0]_CONFIG2
RZ2[3:0]_CONFIG3
RZ2[3:0]_CONFIG2
CZ2[3:0]_CONFIG0
CZ2[3:0]_CONFIG2
CP2[3:0]_CONFIG0
CP2[3:0]_CONFIG3
CZ2[3:0]_CONFIG3
No Registers Exist
PLL2 LOOP FILTER SETTING
Loop Filter Values for PLL2 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV2_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with
PLL2; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3K
+ RZ2[3:0] * 1K , 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ2[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP2[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP2[2:0] A, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
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IDT5V9885TPFGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP
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