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參數(shù)資料
| 型號： | IDT5V9885TPFGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 32TQFP |
| 標準包裝： | 250 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 管件 |
| 其它名稱： | 800-2579 |
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INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
EEPROM INTERFACE
The IDT5V9885T can also store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the
EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit set to "0", followed by the appropriate
command code. The save or restore instruction executes after the STOP condition is issued by the Master, during which time the IDT5V9885T will not generate
Acknowledgebits. TheIDT5V9885Twillacknowledgetheinstructionsafterithascompletedexecutionofthem. Duringthattime,theI2Cbusshouldbeinterpreted
as busy by all other users of the bus.
UsingJTAG,theProgSaveandProgRestoreinstructionsselectstheBYPASSregisterpathforshiftingthedatafromTDItoTDOduringthedataregisterscanning.
During the execution of a ProgSave or ProgRestore instruction, the IDT5V9885T will not accept a new programming instruction (read, write, save, or restore).
All non-programming JTAG instructions will function properly, but the user should wait until the save or restore is complete before issuing a new programming
instruction. Ifanewprogramminginstructionisissuedbeforethesaveorrestorecompletes,thenewinstructionisignored,andtheBYPASSregisterpathremains
in effect for shifting data from TDI to TDO during data register scanning.
The time it takes for the save (TSAVE) and restore (TRESTORE) instructions to complete is:
TSAVE = 100ms max, TRESTORE = 10 ms max
PROGSAVE
PROGRESTORE
NOTE:
PROGWRITE is for writing to the 5V9885T registers.
PROGREAD is for reading the 5V9885T registers.
PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.
S
Address
R/W
ACK Command Code ACK
7-bits
0
1-bit
8-bits:xxxxxx01
1-bit
P
S
Address
R/W
ACK Command Code ACK
7-bits
0
1-bit
8-bits:xxxxxx10
1-bit
P
JTAG INTERFACE
In addition to the IEEE 1149.1 instructions EXTEST, SAMPLE/PRELOAD,
CLAMP, HIGH-Z and BYPASS, the 5V9885T allows access to internal
programmingregistersusingtheREGADDR(setregisteraddress),REGDATAR
(read register) and REGDATW (write register instructions. Data is always
accessedbybyte,andtheregisteraddressincrementsaftereachreadorwrite.
The full instruction set follows. The IDT5V9885T will be updating the registers
during programming.
The JTAG TAP controller can be reset in one of four ways:
1) Power up in JTAG mode
2) Power up in I2C mode and then go into JTAG mode, or go out of and back
into JTAG mode with the I2C/JTAG pin
3) Apply TRST while in JTAG mode
4) Apply five rising edges of TCK with TMS high while in JTAG mode
IR (3)
IR (2)
IR (1)
IR (0)
Instructions
0
EXTEST(1)
0
1
SAMPLE/PRELOAD(1)
0
1
0
IDCODE(1)
0
1
REGADDR(2)
0
1
0
REGDATAW / PROGWRITE(3)
0
1
0
1
REGDATAR / PROGREAD(4)
0
1
0
PROGSAVE(5)
0
1
PROGRESTORE(6)
1
0
CLAMP(1)
1
0
1
HIGHZ(1,7)
1
BYPASS(1)
JTAG INSTRUCTION REGISTER
DESCRIPTION
NOTES:
1. IEEE 1149.1 definition
2. REGADDR is for setting a specific 5V9885T register address.
3. REGDATAW/PROGWRITE is for writing to the 5V9885T registers.
4. REGDATAR/PROGREAD is for reading the 5V9885T registers.
5. PROGSAVE is for saving all the contents of the 5V9885T registers to the EEPROM.
6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9885T registers.
7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9885TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888NLGI | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5V9888NLGI8 | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5V9888TNLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28-VFQFP |
| IDT5V9888TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
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