參數(shù)資料
型號(hào)： IDT5V9885TPFGI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 26/39頁
文件大?。?/td> 0K
描述： IC CLOCK GEN PLL 500MHZ 32TQFP
標(biāo)準(zhǔn)包裝： 250
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 無/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 管件
其它名稱： 800-2579
32
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
RAM (PROGRAMMING REGISTER) TABLES
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-
default); When "11", XTALCAP[7:0] value must also be set to "0".
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
No registers exist.
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State w ill be "Low "));
PLL0 LOOPFILTER SETTING
ADDR
7
6
5
4
3
2
1
0
Register
He x Va lue
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
0
00
MFC
0x05
1
FF
GINEN5
GINEN4
GINE N3
GINEN2
GINEN1
GINEN0
0x06
0
1
0
30
0x07
0
00
0x08
0
00
ODIV0_CONFIG0
0x09
0
00
ODIV0_CONFIG1
0x0A
0
00
ODIV0_CONFIG2
0x0B
0
00
ODIV0_CONFIG3
0x0C
0
00
0x0D
0
00
0x0E
0
00
0x0F
0
00
0x10
0
00
0x11
0
00
0x12
0
00
0x13
0
00
BIT #
D0 [7:0]_CONFIG3
D0 [7:0]_CONFIG0
RZ0[3:0]_CONFIG3
IP0[2:0]_CONFIG3
CP0[3:0]_CONFIG1
CZ0[3:0]_CONFIG0
CP0[3:0]_CONFIG0
CZ0[3:0]_CONFIG1
CZ0[3:0]_CONFIG3
CP0[3:0]_CONFIG2
D0 [7:0]_CONFIG1
CZ0[3:0]_CONFIG2
CP0[3:0]_CONFIG3
D0 [7:0]_CONFIG2
RZ0[3:0]_CONFIG1
Rese rved
IP0[2:0]_CONFIG1
RZ0[3:0]_CONFIG2
IP0[2:0]_CONFIG2
IP0[2:0]_CONFIG0
RZ0[3:0]_CONFIG0
XDRV[1:0]
XTALCAP[7:0]
DES CRIPTION
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typi cal, "11"=XTA L_IN with external clock-default); When
"11", XTA LCAP[7:0] value must also be set to "0".
B its 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL l oad cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
No registers exist
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));
P LL0 LOOP FILTER SETTING
ODIV0_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use wi
P LL0 INPUT DIVIDER D0 SE TTING
0x14
0
00
0x15
0
00
0x16
0
00
0x17
0
00
0x18
0
00
0x19
0
00
0x1A
0
00
0x1B
0
00
0x1C
0
00
SP
SH
OE6
OE5
OE4
OE3
OE 2
OE1
0x1D
0
1
0
40
OKC
OS6
OS5
OS4
OS3
OS 2
OS1
0x1E
0
00
PLLS2
PLLS1
PLLS0
N0 [7:0]_CONFIG0
N0[11:8]_CONFIG0
A0[3:0]_CONFIG3
N0 [7:0]_CONFIG2
A0[3:0]_CONFIG0
A0[3:0]_CONFIG2
A0[3:0]_CONFIG1
N0[11:8]_CONFIG1
N0[11:8]_CONFIG3
N0[11:8]_CONFIG2
N0 [7:0]_CONFIG3
N0 [7:0]_CONFIG1
S P=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);
OE x=Output Di sable Functi on for OUTx, ("1"=OUTx disabled base d on OE pin (De fault for OUT2 -6, Disable mode is defined by OEMx
bits), "0"= Outputs enabled and no association with OE pin (Default));
OS x=Output Power Suspend function for OUTx, ("1"=OUTx will be suspended on GIN3/SUSPEND pin (MFC="1"), "0"= Always Enabled
(Defa ult));
P LLSx=Determines which PLLx to suspend when GIN3 is programmed to be used as SUS PEND, It suspends all the outputs associated
with that PLL, ("1"= suspends based on SUSPEND pin, "0"= PLL enabled and no association with SUSP END pin (Default)); It over-rides
OS x bi ts;
S H=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-ri des OEx and OSx bits, "0"=Ouput
E nable/Disable (Default))
OK C=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:
A ddress 0x1D, Bit 7; Address 0x1E, Bits [7:3] are reserved and should be set to "0"
P LL0 MULTIPLIER SETTING
CONFIG0 will be sele cted if GINx are disabled and operating in MFC mode.
N0[11:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A 0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
S SC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. S ee Spread Spectrum S ettings in register address range
0x60-0x67
Total Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;
(Note : A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
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