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| 型號： | VT8231 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 晶體 |
| 英文描述： | CRYSTAL 8.00MHZ 18PF SMD |
| 中文描述： | 南橋伏特，PC99柔順 |
| 文件頁數(shù)： | 52/132頁 |
| 文件大小： | 1210K |
| 代理商： | VT8231 |
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VT8231
Preliminary Revision 0.8
October 29, 1999
-
46-
Register Descriptions - Legacy I/O Ports
7HFKQRORJLHV,QF
:H &RQQHFW
CMOS / RTC Registers
Port 70 - CMOS Address .................................................. RW
7
NMI Disable
.........................................................RW
0
Enable NMI Generation. NMI is asserted on
encountering IOCHCK# on the ISA bus or
SERR# on the PCI bus.
1
Disable NMI Generation........................default
6-0
CMOS Address
(lower 128 bytes).......................RW
Port 71 - CMOS Data........................................................ RW
7-0
CMOS Data
(128 bytes)
Note:
Ports 70-71 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 70-71 will be directed to an
external RTC.
Port 72 - CMOS Address .................................................. RW
7-0
CMOS Address
(256 bytes).................................RW
Port 73 - CMOS Data........................................................ RW
7-0
CMOS Data
(256 bytes)
Note:
Ports 72-73 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 72-73 will be directed to an
external RTC.
Port 74 - CMOS Address .................................................. RW
7-0
CMOS Address
(256 bytes).................................RW
Port 75 - CMOS Data........................................................ RW
7-0
CMOS Data
(256 bytes)
Note:
Ports 74-75 may be accessed only if Function 0 Rx5B
bit-1 is set to one to enable the internal RTC SRAM
and if Rx48 bit-3 (Port 74/75 Access Enable) is set to
one to enable port 74/75 access.
Note:
Ports 70-71 are compatible with PC industry-
standards and may be used to access the lower 128
bytes of the 256-byte on-chip CMOS RAM. Ports
72-73 may be used to access the full extended 256-
byte space. Ports 74-75 may be used to access the
full on-chip extended 256-byte space in cases where
the on-chip RTC is disabled.
Note:
The system Real Time Clock (RTC) is part of the
“
CMOS
”
block. The RTC control registers are
located at specific offsets in the CMOS data area (0-
0Dh and 7D-7Fh). Detailed descriptions of CMOS /
RTC operation and programming can be obtained
from the VIA VT82887 Data Book or numerous
other industry publications. For reference, the
definition of the RTC register locations and bits are
summarized in the following table:
Offset Description
00
Seconds
01
Seconds Alarm
02
Minutes
03
Minutes Alarm
04
Hours
Binary Range BCD Range
00-3Bh
00-3Bh
00-3Bh
00-3Bh
am 12hr: 01-1Ch
pm 12hr: 81-8Ch
24hr: 00-17h
am 12hr: 01-1Ch
pm 12hr: 81-8Ch
24hr: 00-17h
Day of the Week
Sun=1: 01-07h
Day of the Month
Month
Year
00-59h
00-59h
00-59h
00-59h
01-12h
81-92h
00-23h
01-12h
81-92h
00-23h
01-07h
01-31h
01-12h
00-99h
05
Hours Alarm
06
07
08
09
01-1Fh
01-0Ch
00-63h
0A
Register A
7
6-4
3-0
UIP
DV2-0
Divide (010=ena osc & keep time)
RS3-0
Rate Select for Periodic Interrupt
Update In Progress
0B
Register B
7
6
5
4
3
2
1
0
SET
PIE
AIE
UIE
SQWE
No function (read/write bit)
DM
Data Mode (0=BCD, 1=binary)
24/12
Hours Byte Format (0=12, 1=24)
DSE
Daylight Savings Enable
Inhibit Update Transfers
Periodic Interrupt Enable
Alarm Interrupt Enable
Update Ended Interrupt Enable
0C
Register C
7
6
5
4
3-0
IRQF
PF
AF
UF
0
Interrupt Request Flag
Periodic Interrupt Flag
Alarm Interrupt Flag
Update Ended Flag
Unused (always read 0)
0D
Register D
7
6-0
VRT
0
Reads 1 if VBAT voltage is OK
Unused (always read 0)
0E-7C Software-Defined Storage Registers
(111 Bytes)
Offset Extended Functions
7D
Date Alarm
7E
Month Alarm
7F
Century Field
Binary Range BCD Range
01-1Fh
01-0Ch
13-14h
01-31h
01-12h
19-20h
80-FF Software-Defined Storage Registers
(128 Bytes)
Table 5. CMOS Register Summary
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