參數(shù)資料
型號： IBM3209K4060
英文描述： Telecom Switching Circuit
中文描述： 電信開關(guān)電路
文件頁數(shù)： 52/131頁
文件大?。?/td> 1679K
代理商： IBM3209K4060
PRS28.4G
IBM Packet Routing Switch
Programming Interface and Internal Registers
Page 52 of 131
prs28.03.fm
August 31, 2000
4.3.3 BIST Execution
Built In Self Test (BIST) is initiated via an OCM EVENT command. The system clocks do not need to be
stopped via an OCM EVENT clock control command before BIST is initiated. Two types of BIST may be
executed. An “Auto BIST” which is performed completely by an internal state machine, or a “User Defined
BIST” which lets the user program the BIST cycle count, PRPG seed, and MISR seed.
4.3.3.1 Default BIST
Once Default BIST is initiated the following events occur automatically:
1. The BIST ACTIVE bit in the Status Register is asserted (‘1’b).
2. The primary inputs are forced to a known value and the primary outputs are placed in a high imped-
ance state (I/O isolation).
3. A Flush Reset occurs. This places the device into a known state.
4. The BIST Cycle Count, PRPG and MISR registers are initialized to a known value (starting seeds).
5. BIST is performed.
6. A second Flush Reset occurs.
7. The BIST ACTIVE bit in the Status Register is deasserted (‘0’b).
During BIST, the OCM READ STATUS command should be used to read the Status Register. If the BIST or
Reset active bit is active (‘1’b), the other status bits as well as the parity bit are invalid and should be ignored.
Once BIST is complete, the BIST or Reset Active bit will be inactive ‘0’b. An interrupt will not occur. There-
fore, the BIST or Reset active bit must be polled using the OCM READ STATUS command to determine
when BIST is complete. While BIST is running, the OCM READ STATUS command will not clear the Status
Register. This prevents the BIST signature from being corrupted.
After BIST is completed, the MISR value can be accessed via the Application Registers.
The Default BIST execution time is 4.165 sec (cycle time of 10 ns). This represents a total of 83264 BIST
cycles.
4.3.3.2 User Defined BIST
The BIST Cycle Count register is a count down counter with a completion value of 0. To perform one cycle of
BIST, load the BIST Cycle Count register with a (typical) value of 30 or 100. Before User Defined BIST is initi-
ated the following events must occur:
1. The BIST Cycle Count, PRPG, and MISR registers must be set to a starting value via the Application
Registers 30 and 31.
The User Defined BIST is initiated via an OCM EVENT command. Once User Defined BIST is initiated, the
following events occur automatically:
2. The BIST ACTIVE bit in the Status Register is asserted (‘1’b).
3. The primary inputs are isolated from the core logic and the primary outputs are placed in a high
impedance state (I/O isolation).
4. A Flush Reset occurs, placing the device into a known state.
5. BIST is performed using the user defined values in the BIST Cycle Count, PRPG, and MISR regis-
ters.
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