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| 型號(hào)： | IBM3209K4060 |
| 英文描述： | Telecom Switching Circuit |
| 中文描述： | 電信開關(guān)電路 |
| 文件頁(yè)數(shù)： | 35/131頁(yè) |
| 文件大小： | 1679K |
| 代理商： | IBM3209K4060 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Functional Description
Page 35 of 131
3.3.4 Address Insertion
The input port number is inserted in header byte H1 of incoming Control Packets as follows:
The address insertion field is defined as a 5 bit field. However, in the PRS28.4G bit 3 is forced to 0.
3.4 Input Flow Control
The PRS28.4G continuously maintains shared memory and output queue status information. This status
information is periodically transmitted via the memory grants and output queue grants for flow control to
adapters which are connected to the PRS28.4G inputs.
Flow control is used to signal the adapter that it should stop transmitting packets when the packet memory
threshold is exceeded for the packet-priority or when an output queue threshold is exceeded for the packet
priority.
3.4.1 Memory Threshold Exceeded Condition
There are four programmable memory-full thresholds, one for each packet priority. These thresholds can be
used to prevent packets of a specific priority from using the entire packet memory. When the total number of
allocated memory locations exceeds the threshold value, the corresponding memory grant signal is cleared. It
is set whenever the total number of allocated locations is less than the threshold value.
The four memory-full thresholds must be programmed in decreasing order. That is, the memory-full threshold
for priority 0 must be greater than or equal to the memory-full threshold for priority 1, which in turn must be
greater than or equal to memory-full threshold for priority 2. Consequently, when memory-full threshold 0 is
exceeded, the other memory-full thresholds are also exceeded.
The memory-full information is available on device pins (MEM_GRANT).
3.4.2 Programming the Memory Full Thresholds
The memory-full threshold 0 should be programmed to:
NumberOfPackets - (16 * MasterGrantDelay) - ControlPacketLocations - 32.
32 addresses are reserved by the Input Controller and should be subtracted from the total number of
packets (either 256 or 512 depending whether speed expansion is off or on).
NumberOfPackets is the total packet storage available in shared memory, given in
Speed Expansion
Shared Memory Buffering Capacities
on page 22.
MasterGrantDelay is the reaction delay endured by the Memory grant pin information, calculated in LUs.
The PRS28.4G component of this delay is one LU time. The transmission and processing time of the
Memory Grant by the adapter must be added to this value.
Reserved
0
Input Port
Number
0
1
2
3
4
5
6
7
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