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| 型號(hào)： | IBM3209K4060 |
| 英文描述： | Telecom Switching Circuit |
| 中文描述： | 電信開關(guān)電路 |
| 文件頁(yè)數(shù)： | 5/131頁(yè) |
| 文件大小： | 1679K |
| 代理商： | IBM3209K4060 |
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PRS28.4G
IBM Packet RoutingSwitch
prs28.03TOC.fm
August 31, 2000
Page 5 of 131
5.2.8 Shared Memory Threshold Register 0 ................................................................................... 64
5.2.9 Shared Memory Threshold Register 1 ................................................................................... 65
5.2.10 Mask Register ...................................................................................................................... 66
5.2.11 Synchronization Status and Hunt Register .......................................................................... 67
5.2.12 Sync Packet Transmit Register ........................................................................................... 68
5.2.13 CRC Port ID Register .......................................................................................................... 69
5.2.14 CRC Error Counter .............................................................................................................. 70
5.2.15 NoSignal Register ................................................................................................................ 71
5.2.16 Flow Control Violation Port ID Register ............................................................................... 72
5.2.17 Miscellaneous Status Register ............................................................................................ 73
5.2.18 Output Queue Status Registers 0-3 .................................................................................... 74
5.2.19 Look-Up Tables and Memory Row ...................................................................................... 75
5.2.20 Table Pointer Register ......................................................................................................... 76
5.2.21 Table Data Register ............................................................................................................. 77
5.2.22 Memory Row Address Register ........................................................................................... 78
5.2.23 Command Register .............................................................................................................. 79
5.2.24 Control Packet Destination Register .................................................................................... 80
5.2.25 Bit Map Filter Register ......................................................................................................... 81
5.2.26 Yellow Packet Received Register ........................................................................................ 82
5.2.27 PLL Configuration Register ................................................................................................. 83
5.2.28 Processor Access Registers ................................................................................................ 84
5.2.29 Processor Address Register ................................................................................................ 84
5.2.30 Processor Data Register ..................................................................................................... 85
5.2.31 BIST Data Register .............................................................................................................. 86
5.2.32 BIST Control Register .......................................................................................................... 87
6. Reset, Initialization, and Operation ......................................................................... 88
6.1 Clock and PLL ............................................................................................................................... 88
6.1.1 Internal PLL ........................................................................................................................... 88
6.1.2 External PLL .......................................................................................................................... 88
6.2 Reset .............................................................................................................................................. 88
6.2.1 Power-On-Reset Sequence and Clock Start OCM Event ..................................................... 88
6.2.2 Flush Reset and OCM_RESET Command ........................................................................... 89
6.2.3 nTRST Primary Input Reset .................................................................................................. 89
6.3 Initialization ................................................................................................................................... 89
6.4 DASL Initialization and Operation ............................................................................................... 90
6.5 Control Packet Reception and Transmission ............................................................................. 92
6.5.1 Control Packet Reception ...................................................................................................... 92
6.5.2 Control Packet Transmission ................................................................................................. 93
7. I/O Definitions and Timing ....................................................................................... 94
7.1 I/O Timing ..................................................................................................................................... 105
7.1.1 DASL Signals ...................................................................................................................... 105
7.1.2 OCM Interface Signals ........................................................................................................ 105
7.1.3 Master-Slave Speed Expansion Signals ............................................................................. 108
8. Packaging and Pin Information ............................................................................. 109
9. DASL Specification and Pico-Processor .............................................................. 124
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