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| 型號(hào)： | IBM3209K4060 |
| 英文描述： | Telecom Switching Circuit |
| 中文描述： | 電信開(kāi)關(guān)電路 |
| 文件頁(yè)數(shù)： | 40/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM3209K4060 |
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PRS28.4G
IBM Packet Routing Switch
Functional Description
Page 40 of 131
prs28.03.fm
August 31, 2000
3.8 Packet Transmission
The data stream format at the PRS28.4G output side is identical to the format at the input side. However,
packet transmit start times are synchronized with an internal PRS28.4G packet sync clock, via the SEQ_CLK.
The internal PRS28.4G packet sync clock is either generated internally or can be synchronized with an
external packet sync clock. This is required for a slave device in external speed expansion mode, where the
sync clock of the slaves must be synchronized with the sync clock of the master. The programming of the
SEQ_CLK usage is performed via the Sequencer Sync Pin Mode bit in the Configuration Register 0.
3.8.1 Output Port Servicing
The transmission of a packet on a certain output starts at a fixed time-point, as defined in the table below.
An PRS28.4G output will always transmit a packet. If no Control Packet or Data packet is available to
transmit, or no packet has a transmission grant, then the output will transmit an Idle Packet. Otherwise the
PRS28.4G will transmit the packet.
In external speed expansion, slave outputs start to transmit packets at the same time as master outputs.
Output Port Number
Time Relationship with
SEQ_CLK [byte cycle]
1
Transmission Time without
Internal Speed Expansion
[byte cycle]
Transmission Time
with Internal Speed Expansion
[byte cycle]
0
(reference)
21
0
0
1
25
4
4
2
29
8
8
3
33
12
12
4
22
1
1
5
26
5
5
6
30
9
9
7
34
13
13
8
23
2
-
9
27
6
-
10
31
10
-
11
35
14
-
12
24
3
-
13
28
7
-
14
32
11
-
15
36
15
-
1. The time relationship with SEQ_CLK is the number of clock cycles between a low to high transition on the SEQ_CLK pin and the
start of transmission of the first byte of a packet.
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