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| 型號(hào)： | IBM3209K4060 |
| 英文描述： | Telecom Switching Circuit |
| 中文描述： | 電信開關(guān)電路 |
| 文件頁(yè)數(shù)： | 25/131頁(yè) |
| 文件大小： | 1679K |
| 代理商： | IBM3209K4060 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Functional Description
Page 25 of 131
3. Functional Description
3.1 Logical Interface
As described in
Expansion Modes
on page 22, an PRS28.4G device consists of two switch islands running in
speed expansion. This leads to packet data being carried over an input or output port in two byte streams of
888 Mb/s, one related to the master island, and the other one to the slave island. Each byte stream carries
Logical Units (LU). An LU is a set of bytes belonging to the same packet and which are sent over one stream.
Depending on the expansion mode and packet length, an LU has a length L of 16 to 20 bytes or 32 to 40 (in
step of 2) bytes.
As represented in the figure below, the master LU always carries the packet routing information, or header
bytes, indicated by H0, H1 and H2.
When running in either internal or external speed expansion, two ports are grouped to form a 3.54Gb/s port.
Depending on the port and chip configuration, a 1.77Gb/s port can run either as a master port or a slave port:
The master port is composed of two streams, one master, which carries the packet header information
and data bytes, and one slave, which carries data bytes only.
The slave port is composed of two slave streams, which carry data bytes only.
The LUs of a packet are always transmitted or received at the same time on both streams of a port. Further-
more, the LUs of successive packets are transported one after the other, with no gap between packets.
Figure 5: Packet Format 1.77 Gb/s Port
Figure 6: Packet Format for 3.54 Gb/s Port
H0
H1
H2
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
W0
W1
W2
W3
W4
W5
W6
W(L-1)
D
D
. . .
. . .
. . .
Master LU
Slave LU
16 Bits
H0
H1
H2
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
W0
W1
W2
W3
W4
W5
W6
W(L-1)
D
D
. . .
. . .
. . .
Master LU
Slave LU
16 Bits
Master Port
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
. . .
. . .
Master LU
Slave LU
16 Bits
Slave Port
D
D
D
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