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參數(shù)資料
| 型號(hào)： | HYB18T512800AF-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁(yè)數(shù)： | 103/117頁(yè) |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512800AF-3 |
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Data Sheet
103
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is
recognized as low.
6) The output timing reference voltage level is
V
TT
. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
11) MIN (
t
CL
,
t
CH
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for
t
CL
and
t
CH
).
12) The
t
HZ
,
t
RPST
and
t
LZ
,
t
RPRE
parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (
t
HZ
,
t
RPST
), or begins driving (
t
LZ
,
t
RPRE
).
t
HZ
and
t
LZ
transitions occur in the same access time windows
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
14) 0
≤
T
CASE
≤
85 °C
15) 85 °C
<
T
CASE
≤
95 °C
16) x4 & x8 (1k page size)
17) The
t
RRD
timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
18) x16 (2k page size), not on 256 Mbit component
19) The maximum limit for the
t
WPST
parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
20) Minimum
t
WTR
is two clocks when operating the DDR2-SDRAM at frequencies
≤
200
ΜΗ
z.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD
can be used. In “l(fā)ow active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing
t
XARDS
has to be satisfied.
相關(guān)PDF資料 |
PDF描述 |
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| HYB18T512800AF-3.7 | 512-Mbit DDR2 SDRAM |
| HYB18T512800AF-3S | 512-Mbit DDR2 SDRAM |
| HYB18T512800AC-37 | M39012 MIL RF CONNECTOR |
| HYB18T512800AC-5 | M39012 MIL RF CONNECTOR |
| HYB18T512800AC | DDR2 Registered Memory Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF) |
| HYB18T512800BF-3.7 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF) |
| HYB18T512800BF-3S | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| HYB25D128160AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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