參數(shù)資料
型號: HYB18T512400AF-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 98/117頁
文件大?。?/td> 2102K
代理商: HYB18T512400AF-3
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Data Sheet
98
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
7.2
AC Timing Parameters
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is
recognized as low.
4) The output timing reference voltage level is
V
TT
. See section 8 for the reference load for timing measurements.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x
t
REFI
.
Table 53
Parameter
Timing Parameter by Speed Grade - DDR2-667
Symbol
DDR2-667
Min.
–450
2
0.45
3
0.45
WR +
t
RP
t
IS
+
t
CK
+
t
IH
Unit
Note
1)2)3)4)5)6)
Max.
+450
0.55
0.55
––
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
t
AC
t
CCD
t
CH
t
CKE
t
CL
t
DAL
t
DELAY
ps
t
CK
t
CK
t
CK
t
CK
t
CK
ns
7)
8)
t
DH
(base)
t
DIPW
t
DQSCK
t
DQSL,H
t
DQSQ
t
DQSS
t
DS
(base)
t
DSH
t
DSS
t
HP
t
HZ
t
IH
(base)
t
IPW
175
0.35
–400
0.35
240
– 0.25
100
0.2
0.2
MIN. (
t
CL,
t
CH
)
275
0.6
––
+
400
+ 0.25
ps
t
CK
ps
t
CK
ps
t
CK
ps
t
CK
t
CK
9)
10)
9)
11)
t
AC.MAX
ps
ps
t
CK
12)
9)
t
IS
(base)
t
LZ(DQ)
t
LZ(DQS)
t
MRD
t
OIT
200
2
x
t
AC.MIN
t
AC.MIN
2
0
t
AC.MAX
t
AC.MAX
12
ps
ps
ps
t
CK
ns
9)
12)
12)
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