參數(shù)資料
型號： HYB18T512400AF-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 12/117頁
文件大?。?/td> 2102K
代理商： HYB18T512400AF-3
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Overview
Data Sheet
12
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
1.2
Description
The 512-Mb DDR2 DRAM is a high-speed Double-
Data-Rate-2 CMOS Synchronous DRAM device
containing 536,870,912 bits and internally configured
as a quad-bank DRAM. The 512-Mb device is
organized as either 32 Mbit
×
4 I/O
×
4 banks, 16 Mbit
×
8 I/O
×
4 banks or 8 Mbit
×
16 I/O
×
4 banks chip.
These synchronous devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications. See
Table 3
for performance figures.
The device is designed to comply with all DDR2 DRAM
key features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential
clocks (CK rising and CK falling). All I/Os are
synchronized with a single ended DQS or differential
DQS-DQS pair in a source synchronous fashion.
A 16-bit address bus for
×
4 and
×
8 organised
components and a 15-bit address bus for
×
16
components is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
The
functionality
described
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA package.
and
the
timing
Table 2
Product Type Speed Code
Speed Grade
max. Clock Frequency
High Performance for DDR2–400B and DDR2–533C
–3.7
DDR2–533C 4–4–4
266
266
200
15
15
45
60
–5
DDR2–400B 3–3–3
200
200
200
15
15
40
55
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
@CL5
@CL4
@CL3
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
相關PDF資料
PDF描述
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AF-3 512-Mbit DDR2 SDRAM
HYB18T512800AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512800AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AC-37 M39012 MIL RF CONNECTOR
相關代理商/技術參數(shù)
參數(shù)描述
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應商設備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF)
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