參數(shù)資料
型號(hào)： HYB18T512400AF-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁(yè)數(shù)： 74/117頁(yè)
文件大小： 2102K
代理商： HYB18T512400AF-3
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)當(dāng)前第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
74
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
3.27
Input Clock Frequency Change
During operation the DRAM input clock frequency can
be changed under the following conditions:
During Self-Refresh operation
DRAM is in Precharge Power-down mode and ODT
is completely turned off.
In the Precharge Power-down mode the DDR2-
SDRAM has to be in Precharged Power-down mode
and idle. ODT must be already turned off and CKE must
be at a logic LOW state. After a minimum of two clock
cycles after
t
RP
and
t
AOFD
have been satisfied the input
clock frequency can be changed. A stable new clock
frequency has to be provided, before CKE can be
changed to a HIGH logic level again. After
t
XP
has been
satisfied a DLL RESET command via EMRS(1) has to
be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLL-
re-lock period the DRAM is ready to operate with the
new clock frequency.
Figure 62
Input Frequency Change Example during Precharge Power-Down mode
3.28
Asynchronous CKE LOW Reset Event
In a given system, Asynchronous Reset event can
occur at any time without prior knowledge. In this
situation, memory controller is forced to drop CKE
asynchronously LOW, immediately interrupting any
valid operation. DRAM requires CKE to be maintained
HIGH for all valid operations as defined in this data
sheet. If CKE asynchronously drops LOW during any
valid operation, the DRAM is not guaranteed to
preserve the contents of the memory array. If this event
occurs, the memory controller must satisfy a time delay
(
t
DELAY
) before turning off the clocks. Stable clocks must
exist at the input of DRAM before CKE is raised HIGH
again. The DRAM must be fully re-initialized as
described the initialization sequence (Power On and
Initialization, step 4 through 13). DRAM is ready for
normal operation after the initialization sequence. See
Chapter 7 for
t
DELAY
specification.
Figure 63
Asynchronous Low Reset Event
NOP
NOP
T0
T2
T1
T3
T4
Tx
Tx+1
Ty
CMD
NOP
NOP
NOP
NOP
NOP
DLL
RESET
Ty+2
Ty+3
CKE
Frequency Change
occurs here
NOP
NOP
Frequ.Ch.
Tz
tXP
Stable new clock
before power-down exit
CK, CK
tRP
tAOFD
Minimum 2 clocks
required before
changing the frequency
Ty+1
NOP
Valid
Command
200 clocks
ODT is off during
DLL RESET
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
tdelay
CK, CK
stable clocks
相關(guān)PDF資料
PDF描述
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AF-3 512-Mbit DDR2 SDRAM
HYB18T512800AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512800AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AC-37 M39012 MIL RF CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*