參數(shù)資料
型號(hào): HYB18T512160AF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 111/117頁
文件大?。?/td> 2102K
代理商: HYB18T512160AF
Data Sheet
111
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
–708
–1125
Table 58
Command / Address Slew Rate
(V/ns)
Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533)
CK, CK Differential Slew Rate
2.0 V/ns
t
IS
t
IH
+187
+94
+179
+89
+167
+83
+150
+75
+125
+45
+83
+21
0
0
–11
–14
–25
–31
–43
–54
–67
–83
–110
–125
–175
–188
–285
–292
–350
–375
–525
–500
–800
–1450
Unit
Note
1.5 V/ns
t
IS
+217
+209
+197
+180
+155
+113
+30
+19
+5
–13
–37
–80
–145
–255
–320
–495
–770
–1420
1.0 V/ns
t
IS
+247
+239
+227
+210
+185
+143
+60
+49
+35
+17
–7
–50
–115
–225
–290
–465
–740
–1390
t
IH
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1095
t
IH
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1065
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1)2)
1) For all input signals
t
IS
(total) =
t
IS
(base) +
t
IS
and
t
IH
(total) =
t
IH
(base) +
t
IH
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached V
IH(ac)
/ V
IL(ac)
at the
time of the rising clock) a valid signal is still required to complete the transistion and reach V
IH(ac)
/ V
IL(ac)
. For slew rates in
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3 512-Mbit DDR2 SDRAM
HYB18T512160AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
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