參數(shù)資料
型號： HYB18T512160AF-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 79/117頁
文件大?。?/td> 2102K
代理商： HYB18T512160AF-3
Data Sheet
79
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single
ended or differential mode depending on the setting of
the EMRS(1) “Enable DQS” mode bit; timing
advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin
timing are measured is mode dependent. In single
ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at
V
REF
. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is
verified by design and characterization but not subject
to production test. In single ended mode, the DQS (and
RDQS) signals are internally disabled and don’t care.
Figure 64
Single-ended AC Input Test Conditions Diagram
Table 28
Symbol
DC & AC Logic Input Levels
Parameter
DDR2-400, DDR2-533
Min.
V
REF
+ 0.125
–0.3
V
REF
+ 0.250
—
DDR2-667
Min.
V
REF
+ 0.125
–0.3
V
REF
+ 0.200
—
Max.
V
DDQ
+ 0.3
V
REF
– 0.125
—
V
REF
– 0.250
Max.
V
DDQ
+ 0.3
V
REF
– 0.125
—
V
REF
– 0.200
Unit
V
V
V
V
V
IH(dc)
V
IL(dc)
V
IH(ac)
V
IL(ac)
DC input logic high
DC input low
AC input logic high
AC input low
Table 29
Symbol
V
REF
V
SWING.MAX
SLEW
Single-ended AC Input Test Conditions
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
Value
0.5 x
V
DDQ
1.0
1.0
Unit
V
V
V / ns
Note
1)
1) Input waveform timing is referenced to the input signal crossing through the
V
REF
level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from
V
IH(ac).MIN
to
V
REF
for rising edges and the
range from
V
REF
to
V
IL(ac).MAX
for falling edges as shown in
Figure 64
3) AC timings are referenced with input waveforms switching from
V
IL(ac)
to
V
IH(ac)
on the positive transitions and
V
IH(ac)
to
V
IL(ac)
on the negative transitions.
1)
2)3)
V
DDQ
V
IH (ac) .MIN
V
IH (dc) .MIN
V
REF
V
IL (dc).MAX
V
IL (ac).MAX
V
SS
V
SWING.MAX
delta TR
delta TF
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VREF
- VIL (ac).MAX
delta TF
Falling Slew =
Rising Slew =
VIH(ac).MIN -
delta TR
REF
V
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AF-3 512-Mbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
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