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參數(shù)資料
| 型號： | HYB18T512160AF-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 37/117頁 |
| 文件大小： | 2102K |
| 代理商： | HYB18T512160AF-3 |
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Data Sheet
37
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the
following EMRS(1) mode. In drive mode all outputs are
driven out by DDR2 SDRAM and drive of RDQS is
dependent on EMR(1) bit enabling RDQS operation. In
Drive(1)mode, all DQ, DQS (and RDQS) signals are
driven HIGH and all DQS (and RDQS) signals are
driven LOW. InDrive(0) mode, all DQ, DQS (and
RDQS) signals are driven LOW and all DQS (and
RDQS) signals are driven HIGH. In adjust mode, BL =
4 of operation code data must be used. In case of OCD
calibration default, output driver characteristics have a
nominal impedance value of 18 Ohms during nominal
temperature and voltage conditions. Output driver
characteristics for OCD calibration default are specified
in the following table. OCD applies only to normal full
strength output drive setting defined by EMR(1) and if
half strength is set, OCD default driver characteristics
are not applicable. When OCD calibration adjust mode
is used, OCD default output driver characteristics are
not applicable. After OCD calibration is completed or
driver strength is set to default, subsequent EMRS(1)
commands not intended to adjust OCD characteristics
must specify A[9:7] as’000’ in order to maintain the
default or calibrated value.
OCD impedance adjust
To adjust output driver impedance, controllers must
issue the ADJUST EMRS(1) command along with a 4
bit burst code to DDR2 SDRAM as in the following
table. For this operation, Burst Length has to be set to
BL = 4 via MRS command before activating OCD and
controllers must drive the burst code to all DQs at the
same time. DT0 in the table means all DQ bits at bit
time 0, DT1 at bit time 1, and so forth. The driver output
impedance is adjusted for all DDR2 SDRAM DQs
simultaneously and after OCD calibration, all DQs of a
given DDR2 SDRAM will be adjusted to the same driver
strength setting. The maximum step count for
adjustment is 16 and when the limit is reached, further
increment or decrement code has no effect. The default
setting may be any step within the maximum step count
range. When Adjust mode command is issued, AL from
previously set value must be applied.
Table 13
A9
0
0
0
1
1
Off Chip Driver Program
A8
A7
0
0
0
1
1
0
0
0
1
1
Operation
OCD calibration mode exit
Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low
Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high
Adjust mode
OCD calibration default
Table 14
4 bit burst code inputs to all DQs
DT0
DT1
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
Other Combinations
Off-Chip-Driver Adjust Program
Operation
Pull-up driver strength
NOP (no operation)
Increase by 1 step
Decrease by 1 step
NOP
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Decrease by 1 step
Illegal
DT2
0
0
1
0
0
0
1
0
1
DT3
0
1
0
0
0
1
0
1
0
Pull-down driver strength
NOP (no operation)
NOP
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
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相關(guān)代理商/技術(shù)參數(shù) |
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