參數(shù)資料
型號: HYB18T512160AF-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 54/117頁
文件大?。?/td> 2102K
代理商: HYB18T512160AF-3
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
54
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
Figure 32
Write Operation Example 2
RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
Figure 33
Write followed by Read Example
RL = 5 (AL = 2, CL = 3), WL = 4,
t
WTR
= 2, BL = 4
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 +
t
WTR
, where
t
WTR
is the write-to-read turn-around time
t
WTR
expressed in clock cycles. The
t
WTR
is not a write recovery time (
t
WR
) but
the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
NOP
NOP
NOP
NOP
NOP
WRITE A
Posted CAS
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = RL-1 = 2
BW322
CMD
DQ
NOP
DIN A0
DIN A1
DIN A2
DIN A3
tWR
Completion of
the Burst Write
<= t DQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
CK, CK
NOP
NOP
NOP
NOP
NOP
READ A
Posted CAS
BWBR
CMD
DQ
NOP
DIN A0
DIN A1
DIN A2
DIN A3
AL=2
tWTR
CL=3
NOP
NOP
T0
T2
T1
T3
T4
T5
T6
T7
T8
T9
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
DQS,
DQS
WL = RL - 1 = 4
RL=5
CK, CK
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