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參數資料
| 型號： | HYB18T512160AF-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數： | 33/117頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512160AF-3 |
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Data Sheet
33
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables On-Die termination (ODT) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
Address bit A12 have to be set to 0 for normal
operation. With A12 set to 1 the SDRAM outputs are
disabled and in Hi-Z. 1 on BA0 and 0 for BA1 have to
be set to access the EMRS(1). A13 and all “higher”
address bits have to be set to 0 for compatibility with
other DDR2 memory products with higher memory
densities. Refer to Extended Mode Register Definition.
3.7
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL
enable is required during power up initialization, and
upon returning to normal operation after having the DLL
disabled. The DLL is automatically disabled when
entering Self-Refresh operation and is automatically re-
enabled and reset upon exit of Self-Refresh operation.
Any time the DLL is reset, 200 clock cycles must occur
before a Read command can be issued to allow time for
the internal clock to be synchronized with the external
clock. Failing to wait for synchronization to occur may
result in a violation of the
t
AC
or
t
DQSCK
parameters.
3.8
Output Disable (Qoff)
Under normal operation, the DRAM outputs are
enabled during Read operation for driving data (Qoff bit
in the EMR(1) is set to 0). When the Qoff bit is set to 1,
the DRAM outputs will be disabled. Disabling the
DRAM outputs allows users to measure
I
DD
currents
during Read operations, without including the output
buffer current and external load currents.
3.9
Single-ended and Differential Data Strobe Signals
Table 10
lists all possible combinations for DQS, DQS,
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
in
×
8 components only. If RDQS is enabled in
×
8
components, the DM function is disabled. RDQS is
active for reads and don’t care for writes.
Table 10
EMRS(1)
A11
(RDQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
Single-ended and Differential Data Strobe Signals
Strobe Function Matrix
A10
(DQS Enable)
0 (Enable)
DM
1 (Disable)
DM
0 (Enable)
RDQS
1 (Disable)
RDQS
Signaling
RDQS/DM
RDQS
DQS
DQS
Hi-Z
Hi-Z
RDQS
Hi-Z
DQS
DQS
DQS
DQS
DQS
Hi-Z
DQS
Hi-Z
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
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相關代理商/技術參數 |
參數描述 |
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| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
| HYB18T512400BF-3S | 制造商:Qimonda 功能描述: |
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產品目錄頁面:1449 (CN2011-ZH PDF) |
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