參數(shù)資料
型號(hào)： HT83R074
廠商： Holtek Semiconductor Inc.
英文描述： Q-Voice
中文描述： 調(diào)Q語音
文件頁數(shù)： 16/38頁
文件大?。?/td> 252K
代理商： HT83R074
HT83R074
Rev. 1.00
16
May 17, 2007
The TMR0C is the Timer Counter 0 control register,
which defines the Timer Counter 0 options. The Timer
Counter 1 has the same options as the Timer Counter 0
and is defined by TMR1C.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1 . The
overflow of the timer counter is one of the wake-up
sources.Nomatterwhattheoperationmodeis,writinga
0 to ET0I/ET1I can disable the corresponding interrupt
service.
The TMR0/1 is internal clock source only. There is a
3-bit prescaler (TMRS2, TMRS1, TMRS0) which de-
fines different division ratio of TMR0/1 s clock source.
Time Base
The time base enables the counting operation by
INTC.1 (ETBI) bit. The overflow to interrupt as set
INTC.4. The time base is internal clock source only.
Time base of 1ms to overflow as system clock is 4MHz.
Time base of 0.5ms to overflow as system clock is
8MHz.
The registers states are summarized in the following table.
Register
Reset (Power-on)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR0C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
LATCH0H
---- --xx
---- --uu
---- --uu
---- --uu
---- --uu
LATCH0M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PWMCR
0--- 00-0
u--- uu-u
u--- uu-u
u--- uu-u
u--- uu-u
PWML
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
PWMH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu
uuuu uuuu
VOL
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
LATCHD
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
u means unchanged
x means unknown
means undefined
* -
%
0
: , -
D
# 0 E
%
3
Time Base
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