參數(shù)資料
型號(hào)： HT83R074
廠商： Holtek Semiconductor Inc.
英文描述： Q-Voice
中文描述： 調(diào)Q語(yǔ)音
文件頁(yè)數(shù)： 14/38頁(yè)
文件大?。?/td> 252K
代理商： HT83R074
HT83R074
Rev. 1.00
14
May 17, 2007
Power Down
HALT
The HALT mode is initialized by a HALT instruction
and results in the following:
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and recount
again.
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDToverflow per-
forms a warm reset . By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the CLR WDT instruction, and is set when
the HALT instructionisexecuted.TheTOflagissetifa
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer. The
other maintain their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If awakening from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled by the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, the regular interrupt re-
sponse takes place.
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
Reset
There are 3 ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during any other reset
conditions. Most registers are reset to their initial condi-
tion when the reset conditions are met. By examining
the PDF flag and TO flag, the program can distinguish
between different chip resets .
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
%
(
" 3 % %
Reset Timing Chart
Reset Circuit
%
0
: , -
' ( )
%
/
%
0
5 ( )
%
' (
( %
/
%
(
/
4 /
*
:
3
0
/
Watchdog Timer
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