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參數(shù)資料
| 型號： | HT83R074 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Q-Voice |
| 中文描述： | 調(diào)Q語音 |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 252K |
| 代理商： | HT83R074 |
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HT83R074
Rev. 1.00
13
May 17, 2007
WS7
WS6
WS5
WS4
WS3
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
Interrupt Source
Priority
Vector
Time Base Interrupt
1
04H
Timer Counter 0 Overflow
2
08H
Timer Counter 1 Overflow
3
0CH
Oscillator Configuration
The HT83R074 provides two oscillator circuits for sys-
tem clock, i.e., RC oscillator and Crystal oscillator. No
matter what type of oscillator.. The signal is used for the
system clock. The HALT mode stops the system oscilla-
tor to conserve power. If the RC oscillator is used, an ex-
ternal resistor between OSC1 and VSS is required, and
the range of the resistance should be from 144k
to
275k . The system clock, divided by 4. The RC oscilla-
tor provides the most cost effective solution. However,
the frequency of the oscillation may vary with VDD, tem-
perature, and the chip itself due to process variations. It
is therefore not suitable for timing sensitive operations
where accurate oscillator frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystalacrossOSC1andOSC2isneededtoprovidethe
feedback and phase shift required for the oscillator, and
no other external components are required. Aresonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by options. This timer is
designedtopreventasoftwaremalfunctionorsequence
jumping to an unknown location with unpredictable re-
sults. The Watchdog Timer can be disabled by option. If
the Watchdog Timer is disabled, all the executions re-
lated to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with pe-
riod 78 s normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
IfWS2,WS1,WS0allequalto1,thedivisionratioisupto
1:128,andthemaximumtime-outperiodis2.6seconds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . Whereas in
the HALT mode, the overflow will initialize a warm re -
set only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instruc-
tions, or a HALT instruction. The software instruction
is CLR WDT and execution of the CLR WDT instruc-
tion will clear the WDT.
0 %
0 0
%
0 0
*
*
#
$
, -
System Oscillator
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