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參數(shù)資料
| 型號： | HT83R074 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Q-Voice |
| 中文描述： | 調(diào)Q語音 |
| 文件頁數(shù)： | 12/38頁 |
| 文件大?。?/td> | 252K |
| 代理商： | HT83R074 |
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HT83R074
Rev. 1.00
12
May 17, 2007
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the CLR WDT instruction.
PDF is set by executing the HALT instruction.
5
TO
TO is cleared by system power-up or executing the CLR WDT or HALT instruction.
TO is set by a WDT time-out.
6~7
Unused bit, read as 0
Status (0AH) Register
The Internal Timer Counter 0 Interrupt
is initialized by
setting the Timer Counter 0 interrupt request flag (T0F:bit
5 of INTC), caused by a Timer Counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The Internal Timer Counter 1 Interrupt
is initialized by
setting the Timer Counter 1 interrupt request flag (T1F:bit
6 of INTC), caused by a Timer Counter 1 overflow. When
the interrupt is enabled, and the stack is not full and the
T1F bit is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
Time Base Interrupt
is triggered by set INTC.1 (ETBI)
which sets the related interrupt request flag (TBF:bit 4 of
INTC).Whentheinterruptisenabled,andthestackisnot
fullandtheexternalinterruptisactive,asubroutinecallto
location 04H will occur. The interrupt request flag (TBF)
and EMI bits will be cleared to disable other interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgment are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack
is not full). To return from the interrupt subroutine, the
RET or RETI instruction may be invoked. RETI will
set the EMI bit to enable an interrupt service, but RET
will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The Timer Counter 0/1 interrupt request flag (T0F/T1F)
which enables Timer Counter 0/1 control bit
(ET0I/
ET1I), the time base interrupt request flag (TBF) which
enables time base control bit (ETBI) from the interrupt
control register (INTC:0BH) EMI, ETBI, ET0I, ET1I are
used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt begin ser-
viced. Once the interrupt request flags (T0F, T1F, TBF)
are set, they will remain in the INTC register until the in-
terruptsareservicedorclearedbyasoftwareinstruction.
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well con-
trolled, once a CALL subroutine if used in the interrupt
subroutine will corrupt the original control sequence.
Bit No. Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
ETBI
Controls the time base interrupt
(1= enabled; 0= disabled)
2
ET0I
Controls the timer 0 interrupt
(1= enabled; 0= disabled)
3
ET1I
Controls the timer 1 interrupt
(1= enabled; 0= disabled)
4
TBF
Time base interrupt request flag
(1= active; 0= inactive)
5
T0F
Timer 0 request flag
(1= active; 0= inactive)
6
T1F
Timer 1 request flag
(1= active; 0= inactive)
7
Unused bit, read as 0
INTC (0BH) Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT84036 | Magic VoiceTM |
| HT84XXX | Magic VoiceTM |
| HT84072 | Magic VoiceTM |
| HT84144 | Magic VoiceTM |
| HT84192 | Magic VoiceTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT83V31(24SDIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HT83V31(28SDIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HT83V32(24SDIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HT83V32(28SDIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HT83V33(24SDIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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