HT46R23
Rev. 1.30
8
August 17, 2001
Stack register
STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
Data memory
RAM
The data memory is designed with 224 8 bits. The
data memory is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (192 8). Most are read/write, but some are read
only.
The special function registers include the indirect ad-
dressing registers (00H;02H), timer/event counter
higher-order byte register (TMRH;0CH), timer/event
counter low-order byte register (TMRL;0DH),
timer/event counter control register (TMRC;0EH), pro-
gram counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accu-
mulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC0;
0BH), PWM data register (PWM0;1AH, PWM1;1BH),
the I
2
C BUS slave address register (HADR;20H), the I
2
C
BUS control register (HCR;21H), the I
2
C BUS status regis-
ter (HSR;22H), the I
2
C BUS data register (HDR;23H), the
A/D result lower-order byte register (ADRL;24H), the A/D
result higher-order byte register (ADRH;25H), the A/D con-
trol register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H,
PD;18H) and I/O control registers (PAC;13H, PBC;15H,
PCC;17H, PDC;19H). The remaining space before the
40H is reserved for future expanded usage and reading
theselocationswillget 00H .Thegeneralpurposedata
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
* + ! "' * $
1
3
0
4
8
2
1
3
0
4
8
2
B ( '
-
! - ! C C
/ ( ! "' * $
9 8 , ) :
2 2
1
3
0
4
1 2
( - +)- - + ( % % +)
( - +)- - + ( % % +)
RAM mapping