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參數(shù)資料
| 型號： | HT46R23 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit OTP Microcontroller |
| 中文描述： | 8位微控制器檢察官辦公室 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大?。?/td> | 1172K |
| 代理商： | HT46R23 |
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HT46R23
Rev. 1.30
15
August 17, 2001
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ETI can disable the interrupt
service.
In the case of timer/event counter OFF condition, writ-
ing data to the timer/event counter preload register will
alsoreloadthatdatatothetimer/eventcounter.Butifthe
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
Thetimer/eventcounterwillstilloperateuntiloverflowoc-
curs. When the timer/event counter (reading TMRH) is
read, the clock will be blocked to avoid errors. As clock
blockingmayresultsinacountingerror,thismustbetaken
into consideration by the programmer.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal. The timer prescaler is also
used as the PWM counter.
(Label
Function
PSC0~
PSC2
0~2
To define the prescaler stages, PSC2,
PSC1, PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
TE
3
To define the TMR active edge of timer/
event counter
(0=active on low to high;
1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
TM0
TM1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC register
Input/output ports
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction MOV
A,[m] (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under soft-
ware control. To function as an input, the corresponding
latch of the control register must write 1 . The input
source also depends on the control register. If the con-
trol register bit is 1 , the input will read the pad state. If
the control register bit is 0 , the contents of the latches
will move to the internal bus. The latter is possible in the
read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H or 18H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 3-bit of port C and 6-bit of port D are
not physically implemented; on reading them a 0 is re-
turned whereas writing then results in a no-operation.
See Application note.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by timer/event
counter overflow signal. The input mode always remain-
ing its original functions. Once the PFD option is se-
lected, the PFD output signal is controlled by PA3 data
registeronly.TheI/OfunctionsofPA3are shownbelow.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
PA3
Logical
Input
Logical
Output
Logical
Input
PFD
(Timer on)
Note:
The PFD frequency is the timer/event counter
overflowfrequencydividedby2.
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| HT46R232 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:A/D Type 8-Bit MCU |
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| HT46R321 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:A/D Type 8-Bit OTP MCU with OPA and 8x4 LED Driver |
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