參數(shù)資料
型號: HT46R23
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit OTP Microcontroller
中文描述: 8位微控制器檢察官辦公室
文件頁數(shù): 17/42頁
文件大?。?/td> 1172K
代理商: HT46R23
HT46R23
Rev. 1.30
17
August 17, 2001
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
Modulation cycle i
(i=0~1)
i<AC
DC
1
128
i AC
DC
128
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
F
SYS
/64 for (6+2) bits mode
F
SYS
/128for(7+1)bitsmode
f
SYS
/256
[PWM]/256
A/D converter
The 8 channels and 10-bit resolution A/D (9-bit accu-
racy) converter are implemented in this microcontroller.
The reference voltage is VDD. The A/D converter con-
tains 4 special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D con-
version is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D con-
version control bit and the end of A/D conversion flag. If
the users want to start an A/D conversion. Define PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
1
0). At the end of A/D conversion, the EOC bit is
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
#
E
F G
E
F G
E
F G
E
F G
1
, " #
& $ - ' " ! ) + $ ( * + $ - B3 #
3
3 3
3 3
3 3
3
3
3
3
3
3
3
3 3
3 3
3
3
3 3
3
3 3
3 3
3 3
(6+2) PWM mode
#
E
F G
E
F G
E
F G
E
F G
1
, " #
& $ - ' " ! ) + $ ( * + $ - B4 #
4
4
4
4
4
4
4
4
4
4
4
4
(7+1) PWM mode
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