HT46R23
Rev. 1.30
11
August 17, 2001
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the ROM code option. No matter what oscillator type
is selected, the signal provides the system clock. The
HALT mode stops the system oscillator and ignores an
external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30k
to 750k . The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating fre-
quency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works with a period of
approximately 72 s/5V. The WDT oscillator can be dis-
abled by ROM code option to conserve power.
Watchdog Timer
WDT
TheclocksourceoftheWDTisimplementedbyandedi-
cated RC oscillator (WDT oscillator) or instruction clock
(system clock divided by 4) decided by ROM code op-
tions. This timer is designed to prevent a software mal-
function or sequence jumping to an unknown location
with unpredictable results. The watchdog timer can be
disabled by a ROM code option. If the watchdog timer is
disabled, all the executions related to the WDT result in
no operation.
Once an internal WDT oscillator (RC oscillator with pe-
riod 72 s normally) is selected, it is divided by 2
12
~2
15
(by ROM code option to get the WDT time-out period).
The minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with tem-
perature, VDD and process variations. By selection the
WDT ROM code option, longer time-out periods can be
realized. If the WDT time-out is selected 2
15
, the maxi-
mum time-out period is divided by 2
15
~2
16
about
2.3s~4.7s.
If the WDT oscillator is disabled, the WDT clock may still
cone from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO. Whereas in the halt
mode, the overflow will initialize a warm reset only the
PCandSPareresettozero.ToclearthecontentsofWDT,
three methods are adopted; external reset (a low level to
RES), software instructions, or a HALT instruction. The
softwareinstructionsincludeCLRWDTandtheotherset
, ) ! "
+ " " ! ) $
+ " " ! ) $
* ( ! + (
#
System oscillator
#
4
, ) & " $ =
+ 6 + -
! "
! = ) + $ (
! =
$ * ) + $ (
" )
#
+ & 5 $ ' ))
#
#
#
#
#
#
#
#
3
" !
1
1
Watchdog Timer