HT46R23
Rev. 1.30
18
August 17, 2001
converter circuit is power on. The EOC bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
START should remain at 0 until the EOC is cleared to
0 (end of A/D conversion).
The bit 7 of the ACSR is used for testing purposes only.
It can not be used by the users. The bit1 and bit0 of the
ACSR are used to select A/D clock sources.
Label
(ACSR)
Bits
Function
ADCS0
ADCS1
0
1
Selects the A/D converter clock
source
00= system clock 2
01= system clock 8
10= system clock 32
11= undefined
2~6 Unused bit, read as 0
TEST
7
For test mode used only
ACSR register
Label
(ADCR)
Bits
Function
ACS0
ACS1
ACS2
0
1
2
Defines the analog channel select.
PCR0
PCR1
PCR2
3
4
5
DefinestheportBconfigurationselect.
If PCR0, PCR1 and PCR2 are all zero,
the ADC circuit is power off to reduce
power consumption
EOC
6
Provides response at the end of the
A/D conversion.
(0= end of A/D conversion)
START
7
Starts the A/D conversion. (0
=start; 0
1
reset A/D converter)
1
0
ADCR register
ACS2
ACS1
ACS0
Analog Channel
0
0
0
A0
0
0
1
A1
0
1
0
A2
0
1
1
A3
1
0
0
A4
1
0
1
A5
1
1
0
A6
1
1
1
A7
Analog input channel selection
When the A/D conversion is completed, the A/D inter-
rupt request flag is set. The EOC bit is set to 1 when
the START bit is set from 0 to 1 .
Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL
D1
D0
ADRH
D9
D8
D7
D6
D5
D4
D3
D2
Note: *: D0~D9 is A/D conversion result data bit
LSB~MSB.
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
A0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
A1
A0
0
1
1
PB7
PB6
PB5
PB4
PB3
A2
A1
A0
1
0
0
PB7
PB6
PB5
PB4
A3
A2
A1
A0
1
0
1
PB7
PB6
PB5
A4
A3
A2
A1
A0
1
1
0
PB7
PB6
A5
A4
A3
A2
A1
A0
1
1
1
A7
A6
A5
A4
A3
A2
A1
A0
Port B configuration