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| 型號： | HT46R23 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit OTP Microcontroller |
| 中文描述： | 8位微控制器檢察官辦公室 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 1172K |
| 代理商： | HT46R23 |
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HT46R23
Rev. 1.30
21
August 17, 2001
3: Set EHI bit of the interrupt control register 1 (INTC1)
bit 0 to enable the I
2
C BUS interrupt.
Label
(HSR)
Bits
Function
HCF
7
HCFisclearto 0 whenonedatabyteis
being transferred, HCF is set to 1 indi-
cating 8-bit data communication has
been finished.
HAAS
6
HAAS is set to 1 when the calling ad-
dressed is matched, and I
2
C BUS inter-
rupt will occur and HIF is set.
HBB
5
HBB is set to 1 when I
2
C BUS is busy
and HBB is cleared to 0 means that
the I
2
C BUS is not busy.
4
Unused bit, read as 0
3
Unused bit, read as 0
SRW
2
SRW is set to
wants to read data from the I
2
C BUS, so
the slave must transmit data to the mas-
ter. SRW is cleared to
master wants to write data to the I
2
C
BUS, so the slave must receive data
from the master.
1
when the master
0
when the
1
Unused bit, read as 0
RXAK
0
RXAK is cleared to 0 when the master
receives an 8-bit data and acknowledg-
ment at the 9th clock, RXAK is set to 1
means not acknowledged.
HSR register
Start signal
The START signal is generated only by the master de-
vice. The other device in the bus must detect the START
signal to set the I
2
C BUS busy bit (HBB). The START
signal is SDA line from high to low, when SCL is high.
Slave address
The master must select a device for transferring the
data by sending the slave device address after the
START signal. All device in the I
2
C BUS will receive the
I
2
C BUS slave address (7 bits) to compare with its own
slave address (7 bits). If the slave address is matched,
the slave device will generate an interrupt and save the
following bit (8th bit) to SRW bit and sends an acknowl-
edge bit (low level) to the 9th bit. The slave device also
sets the status flag (HAAS), when the slave address is
matched.
In interrupt subroutine, check HAAS bit to know whether
theI
2
CBUSinterruptcomesfromaslaveaddressthatis
matched or a data byte transfer is completed. When the
slave address is matched, the device must be in trans-
mit mode or receive mode and write data to HDR or
dummy read from HDR to release the SCL line.
SRW bit
The SRW bit means that the master device wants to
read from or write to the I
2
C BUS. The slave device
check this bit to understand itself if it is a transmitter or a
receiver. The SRW bit is set to 1 means that the mas-
terwantstoreaddatafromtheI
2
CBUS,sotheslavede-
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Slave address
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