參數(shù)資料
型號(hào)： HSP50415EVAL1
廠商： Intersil Corporation
英文描述： HSP50415EVAL1 Evaluation Kit
中文描述： HSP50415EVAL1評(píng)估板
文件頁(yè)數(shù)： 6/29頁(yè)
文件大?。?/td> 229K
代理商： HSP50415EVAL1
4-6
kk=(1+(sin(Pm*pi/180)))/(1-(sin(Pm*pi/180)))
wo=2*pi*((Fclk/APLLclkdivider)/Fscale)
A MATLAB or Excel program for calculating the component
values is available. For improved APLL performance,
utilization of specific calculated values is recommended over
the general purpose ones shown in Figure 1.
Symbol NCO
As the data flows through the device, the sample rate
increases up to the final sample rate, with the SYMBOL
NCO generating all of the necessary intermediate sample
rate clocks. Each stage’s input and output sample rate is
dependent on the interpolation rate through the stage.
Figure 1 shows the various symbol clocks that are generated
on the chip. The symbol rate clock (symclk) used internally is
multiplied by 2 and output on pin 2XSYMCLK for use in
driving the input DATACLK if a symbol rate synchronous
(non-burst) mode is required.
The SYMBOL NCO is a 32-bit accumulator. The 32-bit
frequency step (Phinc) is the sum of the user programmable
32-bit symbol Phinc and any error term generated by the
Digital Phase Lock Loop (DPLL) while locking to an external
symbol rate. The DPLL error term may be disabled by a
control bit. The symbol rates supported are from 0.023Hz up
to 25MHz (for FSout of 100MHz) with 32-bit frequency
resolution. The formula for programming the symbol Phinc
register is given as:
symbolPhinc = (symbolRate / FSout) * 2^32
The SYMBOL NCO also has a counter mode in which the
symbol clocks are generated upon the counter reaching the
16-bit user programmable rollover count value. This mode is
useful for cases where the frequency is an integer number of
the system clock (SYSCLK/2).
FIGURE 1. SAMPLE RATE CLK GENERATION
IOUTA
X
SIN(X)
COMPLEX
MIXER
12-BIT
DAC
DATACLK
DIN<15:0>
DATA
FIR
I GAIN
HALFBAND
INT.
FILTER
I GAIN I OFFSET
SYMBOL NCO
2XSYMCLK
X 2
IOUTB
CLK
SYSCLK/2
APLL
BYPASS
sysclk
symclk
(symbol rate)
(symbol rate X 1,2,4,8,16,32)
C1
C2
R1
PLLRC
DC TO 20MHz: C1=690PF, C2=11NF, R1=120
20 TO 100MHz: C1=130PF, C2=2NF, R1=620
Internal IC signal names are shown in lowercase.
÷
2
INTERFACE
FIFO
I
Q
SELECTOR
CONST.
MAP
HSP50415
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參數(shù)描述
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HSP50415VIZ 功能描述:調(diào)節(jié)器/解調(diào)器 W/ANL 100MQFP-40+85C PROGRAMABLE MODLTR RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel
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HSP50B 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS
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