- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385396 > HSP50415EVAL1 (Intersil Corporation) HSP50415EVAL1 Evaluation Kit PDF資料下載
參數(shù)資料
| 型號： | HSP50415EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | HSP50415EVAL1 Evaluation Kit |
| 中文描述： | HSP50415EVAL1評估板 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大小： | 229K |
| 代理商： | HSP50415EVAL1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
4-16
There should be at least 4 digital core clock cycles between
writing to address 4 and reloading the MasterReg as the
data from the MasterReg is being downloaded to slave
registers synchronous to the core clock cycles and
synchronization circuitry is required. The frequency of the
WR pin may not exceed CLK/4 (25MHz max for CLK of
100MHz). To readback the value in control word 12, the
following sequence of writes/reads shown in Table 7 should
occur. Note that the RD pin is the Three-State control for the
CDATA<7:0> bus with a logic 1 on the RD pin disabling the
output drivers configuring the pins as inputs and a logic 0 on
the RD pin enabling the output drivers making the pins
outputs. The CE pin must be active for any read or write to
the device to be processed. The ADDR<2:0>, CDATA<7:0>
and CE pins when writing to the device (RD=1) are
synchronous to the WR pin, but when reading (RD=0), the
ADDR<2:0> and CE pins are not synchronous to the WR
pin, and are actually mux controls to determine which byte of
the read data is output on the CDATA<7:0> bus.:
Writing and reading back the internal RAMs require a
different sequence of writes and reads. Each RAM on the
device is accessible through the uPI, with the FIFO only
having readback capability. The user selects which memory
to access and the access type (read or write) as well as the
address mode by programming the memory configuration bits
in ControlWord 0 as shown in Table 8.
Once these bits are programmed, the user loads up the
masterReg<31:0> using the same sequence as shown in
Table 8 followed by a write to internal address 0x0F to
download the masterReg<31:0> data to the internal memory
word buffer. If auto-increment address mode is selected then
the user does not need to provide the memory address for
the data; the address is generated sequentially internal to
the device. If the 64x72-bit RAMs are selected for the
TABLE 6. SEQUENCE OF WRITES TO LOAD CNTLWORD12
ADDR<2:0
>
CDATA<7:
0>
CE
RD
WR
INTERNAL
OPERATION
0
0xDD
0
1
1
write to
MasterReg<7:0>
1
0xCC
0
1
1
write to
MasterReg<15:8>
2
0xBB
0
1
1
write to
MasterReg<23:16>
3
0xAA
0
1
1
write to
MasterReg<31:24>
4
0x0C
0
1
1
MasterReg<31:0> ->
cntlWord12<31:0>
FIGURE 20. CONTROL REGISTER LOADING SEQUENCE
ADDR<2:0>
CDATA<7:0>
CE
RD
0
WR
1
2
3
4
X
DD
CC
BB
AA
OC
X
TABLE 7. READBACK OF CNTLWORD12
ADDR<2:
0>
CDATA<7:
0>
CE
RD
WR
INTERNAL
OPERATION
5
0x0C
0
1
1
write to addrReg<4:0>
0
0xDD
0
0
x
read
CntlWord12<7:0>
1
0xCC
0
0
x
read
CntlWord12<15:8>
2
0xBB
0
0
x
read
CntlWord12<23:16>
3
0xAA
0
0
x
read
CntlWord12<31:24>
TABLE 8. CONTROL WORD 0 - MEMORY CONTROL BITS
BIT #
VALUE
DEFINITION
7
x
Not Used
6
0
DisableMemoryAddressAutoIncrementMode-
User must provide address
1
Auto-Increment Memory Address Mode Active
5
0
Memory R/W select: Write to Selected Memory
1
Memory R/W select: Read from Selected
Memory
4:2
000
No Memory Access Active
001
I channel 64x72-bit coefficient RAM selected
010
Q channel 64x72-bit coefficient RAM selected
011
I and Q channel 64x72-bit coefficient RAMs
selected for simultaneous access
100
256x8-bit constellation map RAM selected
101
256x32-bit FIFO RAM selected
110
Not Used
111
Not Used
1:0
00
Memory Word Select Bits <1:0>, load with 00
prior to starting load sequence
HSP50415
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP9501 | Programmable Data Buffer(可編程數(shù)據(jù)緩沖器) |
| HSP9520 | Multilevel Pipeline Registers |
| HSP9520CP | Multilevel Pipeline Registers |
| HSP9520CS | Multilevel Pipeline Registers |
| HSP9521 | Multilevel Pipeline Registers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50415VI | 功能描述:調(diào)節(jié)器/解調(diào)器 100MQFP, -40+85C,PROGRAMABLE MODULATOR RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| HSP50415VIZ | 功能描述:調(diào)節(jié)器/解調(diào)器 W/ANL 100MQFP-40+85C PROGRAMABLE MODLTR RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| HSP50A | 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS |
| HSP50B | 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS |
| HSP50SA8 | 制造商:RDI 功能描述:SPEAKER 2 ROUND 8 OHMS CLEAR FACE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。