參數(shù)資料
型號： HSP50415EVAL1
廠商： Intersil Corporation
英文描述： HSP50415EVAL1 Evaluation Kit
中文描述： HSP50415EVAL1評估板
文件頁數(shù)： 18/29頁
文件大?。?/td> 229K
代理商： HSP50415EVAL1
4-18
When writing to the constellation map RAM, when the word
select counter is equal to 0 and a memUpdate strobe occurs,
memBuf<71:64> data is written to memAddr<7:0> of the
constellation map RAM.
When reading back the memories, The sequence is similar
to reading back the Control Words, except the uPI
addresses written to are different. When reading back the
I/Q channel coefficient memories, 9 bytes (72-bits) of data
are read per memory address, the constellation map RAM
contains 1 byte of data per address, while the FIFO RAM
contains 4 bytes of data per address. An internal byte
counter takes care of which byte is being read out with a
write to address 6 with the memory address to be read back
will reset the byte counter to 0. A write to address 7 will
increment the byte counter so the WR clock must be pulsed
during the memory reads in order to increment the byte
counter. Table 11 defines the sequence of writes/reads
necessary to read back the I channel coefficient memory
data at memory address 0x12.
The constellation map RAM and the FIFO RAM are read
back in a similar manner with fewer writes to address 7 since
fewer bytes per address are read back.
A synopses of the uPI address space functions is shown in
Table 12, with Tables 13-32 providing detailed descriptions.
TABLE 11. EXAMPLE SEQUENCE OF WRITES TO READ I COEFFICIENT RAM
ADDR<2:0>
CDATA<7:0>
CE
RD
WR
INTERNAL OPERATION
MEM BYTE
COUNT<3:0>
0
0x24
0
1
1
write to MasterReg<7:0>
xx
4
0x00
0
1
1
MasterReg<7:0> -> cntlWord0<7:0>
xx
6
0x12 (memAddr)
0
1
1
write to memReadAddr<7:0>
0
6
0x12 (memAddr)
0
1
1
write to memReadAddr<7:0>
0
7
memData[18][7:0]
0
0
1
read memData[18] byte 0
0
7
memData[18][15:8]
0
0
1
read memData[18] byte 1
1
7
memData[18][23:16]
0
0
1
read memData[18] byte 2
2
7
memData[18][31:24]
0
0
1
read memData[18] byte 3
3
7
memData[18][39:32]
0
0
1
read memData[18] byte 4
4
7
memData[18][47:40]
0
0
1
read memData[18] byte 5
5
7
memData[18][55:48]
0
0
1
read memData[18] byte 6
6
7
memData[18][63:56]
0
0
1
read memData[18] byte 7
7
7
memData[18][71:64]
0
0
1
read memData[18] byte 8
8
TABLE 12. MICROPROCESSOR INTERFACE ADDRESS SPACE DEFINITIONS
ADDR <2:0>
WR/RD
INTERNAL OPERATION
0
wr
Write to MasterReg<7:0> (CDATA<7:0> -> MasterReg<7:0>)
1
wr
Write to MasterReg<15:8> (CDATA<7:0> -> MasterReg<15:8>)
2
wr
Write to MasterReg<23:16> (CDATA<7:0> -> MasterReg<23:16>)
3
wr
Write to MasterReg<31:24> (CDATA<7:0> -> MasterReg<31:24>)
4
wr
Download MasterReg<31:0> -> Control Word x (x=CDATA<4:0>)
5
wr
Write address of Control Word to be read back (CDATA<4:0> -> addrReg<4:0>)
6
wr
Write address of Accessed Memory to be read back (CDATA<7:0> -> memAddr<7:0>)
7
wr
Increment Memory Address Read Back Byte Counter (byteCount<3:0>)
0
rd
Read ControlWordx<7:0> (x=addrReg<4:0>)
1
rd
Read ControlWordx<15:8> (x=addrReg<4:0>)
2
rd
Read ControlWordx<23:16> (x=addrReg<4:0>)
3
rd
Read ControlWordx<31:24> (x=addrReg<4:0>)
4
rd
Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0>)
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