參數(shù)資料
型號(hào)： HSP50415EVAL1
廠商： Intersil Corporation
英文描述： HSP50415EVAL1 Evaluation Kit
中文描述： HSP50415EVAL1評(píng)估板
文件頁(yè)數(shù)： 21/29頁(yè)
文件大?。?/td> 229K
代理商： HSP50415EVAL1
4-21
TABLE 16. FIFO AND I/O CONTROL
ADDRESS = 02
H
BIT NO.
DESCRIPTION
RESET STATE
31:24
FIFO Frequency Term 4 Loop Filter <7:0>.
00
H
23
FIFO Full Stop Writing
0
22
FIFO Empty, Force 0 data
0
21:20
FIFO Threshold Mode
00
B
= Disable Threshold Logic and FIFOUnderFlow / FIFOOverFlow flags
01
B
= Enable Thresholds, Disable Symbol Rate Modifications
10
B
= Enable Thresholds and Modify Frequency Error Term
11
B
= Enable Thresholds and Force lag accumulator to Limit
00
B
19
FIFO TXEN Zero Data. (Function: If FIFO Reads are gated with TXEN Pin then force data out of FIFO
block to 0x0000 if TXEN is inactive.)
0
18
FIFO TXEN Enable Gated Write
0 = TXEN Pin gates writing to FIFO
1 = FIFO writes not gated by TXEN
0
17
FIFO TXEN Gated Read
0 = FIFO reads not gated by TXEN (reads begin after 2 FIFO locations written)
1 = TXEN Pin gates read from FIFO
0
16
FIFO Underflow/Empty Pin Function
0 = Output FIFO underflow status on Pin FEMPT
1 = Output FIFO empty status on Pin FEMPT
0
15
2XSYMCLK polarity
0
14
2XSYMCLK Three-State enable
0 = off
1 = enable output
0
13
FFULL, FIFO Full Output Enable
0
12
FOVRFL, FIFO Overflow Output Enable
0
11
FEMPT, FIFO Under/Empty Output Enable
0
10
LOCKDET Output Enable
0
9
SYSCLK/2 Output Enable
0
8
INTREQ Pin Output Enable
0
7
IOUT<13:0> Output Enable
0
6
QOUT<13:0> Output Enable
0
5
TXEN Polarity
0 = Active High
1 = Active Low
0
4
ISTRB Polarity.
0 = Active High (DIN<15:0> contains Isample when ISTRB is high)
1 = Active Low (DIN<15:0> contains Isample when ISTRB is low)
0
3
SYSCLK/2 polarity.
0 = IOUT<13:0>/QOUT<15:0> data out on falling edge
1 = IOUT<13:0>/QOUT<15:0> data out on rising edge
0
2
FIFO Gated Read No Address Reset
0
1
IDAC Power Enable
0
0
QDAC Power Enable
0
HSP50415
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