- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385396 > HSP50016 (Intersil Corporation) Digital Down Converter(數(shù)字式下變頻轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | HSP50016 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital Down Converter(數(shù)字式下變頻轉(zhuǎn)換器) |
| 中文描述： | 數(shù)字下變頻器（數(shù)字式下變頻轉(zhuǎn)換器） |
| 文件頁數(shù)： | 24/30頁 |
| 文件大?。?/td> | 258K |
| 代理商： | HSP50016 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁
3-24
Quadrature Spectral Reversal
Spectral reversal is often used to negate a spectral reversal
which has occurred due to a previous operation in the
processing chain. Examples of this are spectral reversal in
an analog down conversion or in a constructive aliasing
operation. The DDC gives the user the ability to convert the
signal to baseband in either forward or reverse fashion.
Quadrature spectral reversal is achieved by translating the
lower sideband of the input to baseband rather than the
upper sideband. This is implemented in the DDC by mixing
the input signal with e
j2
π
f
c
n
- that is, up converting the input
rather than down converting it. The resulting signal is:
Assuming x(n) = cos(
ω
k
n),
(n) = cos(
ω
k
n)[cos(
ω
c
n) + jsin(
ω
c
n)]
= [cos((
ω
k
-
ω
c
)n) + cos((
ω
k
+
ω
c
)n)
+ j(sin((
ω
k
+
ω
c
)n) - sin((
ω
k
-
ω
c
)n))]
After quadrature filtering and correcting for the gain of 1/2,
we have:
The appropriate spectral plots are shown in Figure 19. In up
conversion, the sine output of the SIN/COS Generator is
negated so that the vector output of the Local Oscillator
rotates counter clockwise. This is implemented by setting the
Spectral Reverse bit in Control Word 4 to a one. Otherwise,
the setup for this mode is the same as the one for down
conversion.
Real Spectral Reversal
Real spectral reversal is simply quadrature spectral
reversal with quadrature to real conversion in the
Formatter. The up converted and filtered signal w(n) is
upconverted again by f”/4 in the Formatter. Each sideband
of the result is spectrally reversed from the sidebands that
would have been produced by down conversion with
quadrature to real conversion. The output spectrum is
shown in Figure 20.
The setup for this application is similar to that of down
conversion, except in Control Word 4, where the Spectral
Reverse and Real Output bits are set to one.
High Decimation Filter Only
The DDC can be operated as a single high decimation
filter. This is done by setting the Phase Generator to Filter
Only and the Minimum Phase Increment and Phase Offset
to 0. This multiplies the incoming data stream by a constant
hexadecimal 3FFFF in the I channel and 0 in the Q
channel. The HDF Section of the circuit requires a
minimum decimation rate of 16 to allow sufficient time for
the FIR to compute its response. This mode of operation
implements a filter which has a decimation rate from 64 to
131,072. The frequency response is shown in Figures 7, 8
and 9. Only the I output has valid data in this mode; the Q
output should be set to high impedance state to reduce
circuit noise.
Multichannel Operation
Several DDCs can be placed in parallel with each one
operating on a different frequency band. To minimize
wiring, their outputs can be configured so that they are
connected over a common serial bus. Each DDC is
assigned a time slot number (Control Word 6) and a time
slot length (Control Word 3). Each DDC in turn controls the
bus for long enough to output its data, then relinquishes the
bus. The time slot assignment and length are programmed
at configuration time. Up to 64 chips can be multiplexed in
this manner.
u(n)= x(n)e
j2
π
f
c
n
= x(n)[cos(
ω
c
n) + jsin(
ω
c
n)]
(EQ. 27)
(EQ. 28)
w(n) = cos((
ω
k
-
ω
c
)n) - jsin((
ω
k
-
ω
c
)n)
= cos(-(
ω
k
-
ω
c
)n) + jsin(-(
ω
k
-
ω
c
)n)
= cos((
ω
c
-
ω
k
)n) + jsin((
ω
c
-
ω
k
)n)
= e
j(
ω
c
-
ω
k
)n
(EQ. 29)
ω
C
-
ω
C
A. INPUT SIGNAL SPECTRUM
B. UP CONVERSION AND FILTERING
FIGURE 19. UP CONVERSION OF FILTER OUTPUT SIGNAL
0
f”/4 f”/2
-f”/4
-f”/2
C. SECOND OPERATION IN FORMATTER: I OUTPUT = I + Q
B. FIRST OPERATION IN FORMATTER:
UP CONVERT BY SAMPLE FREQUENCY / 4
0 f”/4 f”/2
-f”/4
-f”2
A. OUTPUT OF FILTERS: SIGNAL OVERSAMPLED BY 2
0 f”/4 f”/2
-f”/4
-f”/2
FIGURE 20. QUADRATURE TO REAL CONVERSION OF AN
OUTPUT SIGNAL
HSP50016
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50110JI-52 | Digital Quadrature Tuner |
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50016_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Down Converter |
| HSP50016-EV | 制造商:Rochester Electronics LLC 功能描述:HSP50016 EVALUATION PLATFORM - Bulk |
| HSP50016GC-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50016JC-52 | 功能描述:上下轉(zhuǎn)換器 DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50016JC-5296 | 制造商:Rochester Electronics LLC 功能描述:TAPE AND REEL OF HSP50016JC-52 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。