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參數(shù)資料
| 型號： | HSP50016 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital Down Converter(數(shù)字式下變頻轉換器) |
| 中文描述： | 數(shù)字下變頻器（數(shù)字式下變頻轉換器） |
| 文件頁數(shù)： | 2/30頁 |
| 文件大小： | 258K |
| 代理商： | HSP50016 |
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3-2
Pinout
44 LEAD PLCC
TOP VIEW
Pin Description
NAME
TYPE
DESCRIPTION
V
CC
GND
-
+5V Power.
-
Ground.
DATA0-15
I
Input Data Bus. Selectable between two's complement and offset binary. DATA0 is the LSB.
CLK
I
Clock for input data bus. f
S
is the frequency of CLK, which is also the input sample rate.
RESET initializes the internal state of the DDC. During RESET, all internal processing stops. RESET
facilitates the synchronization of multiple chips for Auto Three-State operation. If the Force bits in Control
Word 7 are inactive and the IEEE Test Access Port is in an Idle state, RESET causes the IQCLK, IQSTB,
I and Q outputs to go to a high impedance state.
RESET
I
All Control Registers are updated from their respective Control Buffer Registers on the third rising edge
of CLK after the deassertion of RESET. If RESET is deasserted t
RS
nanoseconds prior to the rising edge
of CLK, the internal reset will deassert synchronously. If t
RS
is violated, then the circuit contains a syn-
chronizer which will cause reset to be deasserted internally one or more clocks later.
An initial reset is required to guarantee proper operation of the DDC. Active low.
I
O
The I output has three modes: I data; I data followed by Q data; real data.
Q
O
The Q output has two modes: Q data and the carry out of the Phase Adder.
IQCLK
O
IQ Clock: Bit or word clock for the I and Q outputs.
IQSTB
O
IQ Strobe: Beginning or end of word indicator for I and Q.
IQSTRT
I
IQ Start: Initiates output data sequence. Active low.
CDATA
I
Control Data: Port for control data input.
CCLK
I
Control Data Clock: Control data input bit clock.
CSTB
I
Control Data Strobe: Beginning of word indicator for control data.
CS
I
Chip Select: Enables control data loading of DDC. Active low.
TCK
I
Test Clock: Bit Clock for IEEE 1149.1 Data. This signal should be either tied low or pulled high when the
TAP is not used.
TMS
I
Test Port Mode Select: This signal should be either left unconnected or pulled high when the TAP is not
used.
TDI
I
Test Data Input for IEEE Test Port: This signal should be either left unconnected or pulled high when the
TAP is not used.
TDO
O
Test Data Output for IEEE Test Port: This output will be in the high impedance state when the TAP is
not used.
TRST
I
Test Port Reset. Active Low. This signal should be tied low when the TAP is not used.
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
20 21 22 23 24 25 26
19
18
7
8
9
10
11
12
13
14
15
16
17
V
C
G
T
T
T
V
C
T
T
R
G
V
C
GND
DATA15
DATA14
DATA13
DATA12
GND
DATA11
DATA10
DATA9
DATA8
DATA7
V
CC
DATA6
DATA5
DATA4
DATA3
V
CC
GND
CLK
DATA2
DATA1
DATA0
G
Q
I
I
I
I
C
C
C
C
V
C
HSP50016
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50110JI-52 | Digital Quadrature Tuner |
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數(shù)字調諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50016_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Down Converter |
| HSP50016-EV | 制造商:Rochester Electronics LLC 功能描述:HSP50016 EVALUATION PLATFORM - Bulk |
| HSP50016GC-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50016JC-52 | 功能描述:上下轉換器 DIGITAL DOWN CONVERTER 44 PLCC, 52MHZ, COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50016JC-5296 | 制造商:Rochester Electronics LLC 功能描述:TAPE AND REEL OF HSP50016JC-52 - Bulk |
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